S3028
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for
diagnostic purposes. The differential serial output data
from the transmitter is routed to the serial-to-parallel
block in place of the normal data stream (RSD).
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
For operation at 19.44 MHz and 51.84 MHz refer-
ences, separate timing paths are use for PLL control
and PCLK generation, and forward clocking is not
recommended.
"Squelched Clock" Operation
Some integrated optical receiver/clock recovery
modules force their recovered serial receive clock
output to the logic zero state if the optical signal is
removed or reduced below a fixed threshold. This
condition is accompanied by the expected
deassertion of the signal detect output.
The S3028B has been designed for operation with
clock recovery devices that provide continuous serial
clock for seamless down stream clocking in the
event of optical signal loss. For operation with an
optical transceiver that provides the “squelched
clock” behavior as described above, the S3028B can
be operated in the “squelched clock mode” by set-
ting the BUSWIDTH input low, (4 bit mode at 155.52
Mbit/s rate) while the MODE input is set high (622.08
Mbit/s rate). "Squelched Clock" mode is available in
622.08 Mbit/s mode only.
The Receive Serial Clock, RSCLKP/N, is used for all
receiver timing when the SDPECL/SDTTL inputs are
in the active state. When the SDPECL/SDTTL inputs
are placed in the inactive state, (usually by the
deassertion of LOCKDET or signal detect from the
optical transceiver/clock recovery unit) the transmit-
ter serial clock will be used to maintain timing in the
receiver section. This will allow the POCLK to con-
tinue to run and the parallel outputs to flush out the
last received characters and assume the all zero
state imposed at the serial data input.
In this mode there will be a random 1.6 nsec short-
ening or lengthening of the POCLK cycle, resulting
in an apparent phase shift in the POCLK at the
deassertion of the signal detect condition. Another
similar phase shift will occur when the signal detect
condition is reasserted.
In the normal operating mode with both MODE and
BUSWIDTH inputs high, there will be no phase
discontinuities at the POCLK output during signal
loss or reacquisition (assuming operation with con-
tinuous clocking from the CRU device such as the
AMCC S3026 or S3027)
Line Loopback
The line loopback circuitry consists of alternate clock
and data output drivers. For the S3028, it selects the
source of the data and clock which is output on TSD
and TSCLK. When the Line Loopback Enable
(LLEB) input is inactive, it selects data and clock
from the parallel to serial converter block. When
LLEB is active, it forces the output data multiplexer
to select data and clock from the RSD and RSCLK
inputs, and a receive-to-transmit loopback can be
established at the serial data rate. Diagnostic
loopback and line loopback can be active at the
same time.
Loop Timing
In loop timing mode, the clock synthesizer PLL of the
S3028 is bypassed, and the timing of the entire
transmitter section is controlled by the Receive Se-
rial Clock, RSCLKP/N. This mode is entered by
setting the TESTEN input to a TTL high level.
The internal PLL continues to operate in this mode,
and continues as the source for the 19MCK. If this
signal is being used (e.g. as the reference for an
external clock recovery device such as the AMCC
S3026), the REFCLKP/N and REFSEL[1:0] inputs
must be properly driven in either 19.44 MHz or 51.84
MHz mode. The 19MCK output should not be used
in loop timing mode if 77.76 or 38.88 MHz reference
operation is selected. The MODE input has no effect
on the transmitter operation if loop timing is selected.
Forward Clocking
For both 77.76 MHz and 38.88 MHz reference op-
eration, the S3028 operates in the forward clocking
mode. The PLL locks the PCLK output of the trans-
mitter section to the REFCLK with a fixed and
repeatable phase relation. This allows the transmitter
data source to also be the timing source for the se-
rial clock synthesis.
6
December 13, 1999 / Revision H
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
