SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3017/S3018 OVERVIEW
The S3017 transmitter and S3018 receiver implement
SONET/SDH serialization/deserialization, transmission,
and frame detection/recovery functions. The block dia-
grams in Figures 4 and 5 show basic operation of both
chips. These chips can be used to implement the front
end of SONET equipment, which consists primarily of
the serial transmit interface (S3017) and the serial
receive interface (S3018). The chipset handles all the
functions of these two elements, including parallel-to-
serial and serial-to-parallel conversion, clock generation
and recovery, and system timing. The system timing
circuitry consists of management of the datastream,
framing, and clock distribution throughout the front end.
Operation of the S3017/S3018 chips is straightforward.
The sequence of operations is as follows:
Transmitter
1. 8-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
S3017/S3018
Receiver
1. Clock and data recovery from serial input
2. Frame detection
3. Serial-to-parallel conversion
4. 8-bit parallel output
Internal clocking and control functions are transparent
to the user. Details of data timing can be seen in Figures
9 through 14.
A lock detect feature is provided on the S3018, which
indicates that the PLL is locked (synchronized) to the
data stream, and facilitates continuous down-stream
clocking in the absence of data.
Suggested Interface Devices
AMCC CONGO (S1201)
AMCC NILE
(S1202)
AT&T ASTROTEC1227/1230
Mitsubishi MF-622DF-T12-XXX
Sumitomo ES-9304-TD
AT&T ASTROTEC 1310
Sumitomo ES-9216-RD
Finisar
POS/ATM SONET Mapper
ATM SONET Mapper
650 Mbit/s
622 Mbit/s
622 Mbit/s
650 Mbit/s
622 Mbit/s
Fiber Optic Transmitter
Fiber Optic Transmitter
Fiber Optic Transmitter
Fiber Optic Receiver
Fiber Optic Receiver
Fiber Optic Receiver
Mitsubishi MF-622DS-R1X-XXX 622 Mbit/s
1000 Mbit/s Fiber Optic Transceiver
Figure 4. S3017 Transmitter Functional Block Diagram
TSCLKSEL
LOCLPEN
2
8
8:1 PARALLEL
TO SERIAL
PICLK
D
2
LPDATOP/N
SERDATOP/N
PIN[7:0]
PCLK
TIMING
GEN
TSTCLKEN
REFSEL
REFCKINP/N
2
CLOCK
SYNTHESIZER
RSTB
TESTRST
CAP1
CAP2
December 10, 1999 / Revision B
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
