S3017/S3018
S3018 RECEIVER
FUNCTIONAL DESIGN
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
This transfer function yields a typical capture time of 16
µs
for random incoming NRZ data. A single external
clean-up capacitor is utilized as part of the loop filter.
The total loop dynamics of the clock recovery PLL yield a
jitter tolerance which meets, with ample margin, the mini-
mum tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 6.
Backup Reference Generator
The Backup Reference Generator seen in Figure 5 pro-
vides backup reference clock signals to the clock recovery
block when the clock recovery block detects a loss of
signal condition. It contains a counter that divides the
clock output from the clock recovery block down to the
same frequency as the reference clock REFCKINP/N.
Frame and Byte Boundary Detection
The S3018 receiver chip provides the first stage of
digital processing of a receive SONET STS-12 bit-serial
stream. It converts the bit-serial 622.08 Mbit/sec data
stream into a 77.76 Mbyte/sec byte-serial data format.
Clock recovery is performed on the incoming scrambled
NRZ data stream. A 77.76 MHz reference clock is
required for phase locked loop start-up and proper
operation under loss of signal conditions. An integral
prescaler and phase locked loop circuit is used to
multiply this reference to the nominal bit rate.
A loopback mode is provided for diagnostic loopback
(transmitter to receiver), when used with the compatible
S3017 device.
Clock Recovery
The Clock Recovery PLL, as shown in the block diagram
in Figure 5, generates a clock that is at the same frequency
as the incoming data bit rate at the SERDATI or LPDATI
inputs. The clock is phase aligned by a PLL so that it
samples the data in the center of the data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared
by a phase/frequency discriminator. Output pulses from
the discriminator indicate the required direction of phase
corrections. These pulses are smoothed by an integral
loop filter. The output of the loop filter controls the
frequency of the Voltage Controlled Oscillator (VCO),
which generates the recovered clock. Frequency stabil-
ity without incoming data is guaranteed by an alternate
reference input (REFCKIN) that the PLL locks onto
when data is lost.
The clock recovery circuit monitors the incoming data
stream for loss of signal. If the incoming data stream has
had no transitions for between 96 and 224 bit times
(depending upon the state of an internal counter at the
time of last transistion), loss of signal is declared and the
PLL will switch from locking onto the incoming data to
locking onto the reference clock. Alternatively, the loss-
of-signal (LOS) input can be used to force a loss-of-signal
condition. When set high, LOS squelches the incoming
data stream, and thus causes the PLL to switch its
source of reference within 128 bit times. Loss-of-signal
condition is removed when LOS is low, and good data,
with acceptable pulse density and run length, returns on
the incoming data stream.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transi-
tion density expected in a received SONET data signal.
The Frame and Byte Boundary Detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. Framing pattern detection is enabled and dis-
abled by the out-of-frame (OOF) input. Detection is
enabled by a rising edge on OOF, and remains enabled
for the duration that OOF is set high. It is disabled when
a framing pattern is detected and OOF is no longer set
high. When framing pattern detection is enabled, the
framing pattern is used to locate byte and frame bound-
aries in the incoming data stream (SERDATI or LPDATI).
The timing generator block takes the located byte
boundary and uses it to block the incoming data stream
into bytes for output on the parallel output data bus
(POUT[7:0]). The frame boundary is reported on the
frame pulse (FP) output when any 48-bit pattern match-
ing the framing pattern is detected on the incoming data
stream. When framing pattern detection is disabled, the
byte boundary is frozen to the location found when
detection was previously enabled. Only framing pat-
terns aligned to the fixed byte boundary are indicated on
the FP output.
The probability that random data in an STS-12 stream
will generate the 48-bit framing pattern is extremely
small. It is highly improbable that a mimic pattern would
occur within one frame of data. Therefore, the time to
match the first frame pattern and to verify it with down-
stream circuitry, at the next occurrence of the pattern, is
expected to be less than the required 250
µs,
even for
extremely high bit error rates.
Once down-stream overhead circuitry has verified that
frame and byte synchronization are correct, the OOF
input can be set low to disable the frame search process
from trying to synchronize to a mimic frame pattern.
6
December 10, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
