QUAD GIGABIT ETHERNET DEVICE
RECEIVER DESCRIPTION
S2204
The “lock to reference” frequency criteria ensure that
the S2204 will respond to variations in the serial data
input frequency (compared to the reference fre-
quency). The new Lock State is dependent upon the
current lock state, as shown in Table 4.
Each receiver channel is designed to implement a
Serial Backplane receiver function through the physi-
cal layer. A block diagram showing the basic func-
tion is provided in Figure 5.
The run-length criteria insure that the S2204 will re-
spond appropriately and quickly to a loss of signal.
The run-length checker flags a condition of consecu-
tive ones or zeros across 12 parallel words. Thus
119 or less consecutive ones or zeros does not
cause signal loss, 129 or more causes signal loss,
and 120 - 128 may or may not, depending on how
the data aligns across byte boundaries.
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2204 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the word-aligned data on its parallel outputs.
If both the off-frequency detect circuitry test and the
run-length test are satisfied, the CRU will attempt to
lock to the incoming data. It is possible for the run
length test to be satisfied due to noise on the inputs,
even if no signal is present. In this case the receiver
VCO will maintain frequency accuracy to within 100
ppm of the target rate as determined by REFCLK.
Data Input
A differential input receiver is provided for each chan-
nel of the S2204. Each channel has a loopback mode
in which the serial data from the transmitter replaces
external serial data. The loopback function for each
channel is enabled by its respective LPEN input.
In any transfer of PLL control from the serial data to
the reference clock, the RBC1/0x outputs remain
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
The high speed serial inputs to the S2204 are inter-
nally biased to VDD-1.3V. All that is required exter-
nally are AC-coupling and line-to-line differential
termination.
Reference Clock Input
Clock Recovery Function
A single reference clock, which serves both transmit-
ter and receiver, must be provided from a low jitter
clock source. The frequency of the received data
stream (divided-by -10 or -20) must be within 200
ppm of the reference clock to insure reliable locking
of the receiver PLL.
Clock recovery is performed on the input data
stream for each channel of the S2204. The receiver
PLL has been optimized for the anticipated needs of
Serial Backplane systems. A simple state machine in
the clock recovery macro decides whether to acquire
lock from the serial data input or from the reference
clock. The decision is based upon the frequency and
run length of the serial data inputs. If at any time the
frequency or run length checks are violated, the
state machine forces the VCO to lock to the refer-
ence clock. This allows the VCO to maintain the cor-
rect frequency in the absence of data.
Serial to Parallel Conversion
Once bit synchronization has been attained by the
S2204 CRU, the S2204 must synchronize to the 10
bit word boundary. Word synchronization in the
S2204 is accomplished by detecting and aligning to
the 8B/10B K28.5 codeword. The S2204 will detect
and byte-align to either polarity of the K28.5. Each
channel of the S2204 will detect and align to a K28.5
anywhere in the data stream. The presence of a
K28.5 is indicated for each channel by the assertion
of the COM_DETx signal.
Table 4. Lock to Reference Frequency Criteria
Current Lock
State
PLL Frequency
(vs. REFCLK)
New Lock State
< 488 ppm
488 to 732 ppm
> 732 ppm
Locked
Undetermined
Unlocked
Locked
< 244 ppm
Locked
Unlocked
244 to 366 ppm
> 366 ppm
Undetermined
Unlocked
9
October 9, 2000 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
