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S2204TB 参数 Datasheet PDF下载

S2204TB图片预览
型号: S2204TB
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 4-Trnsvr, CMOS, PBGA208, 23 X 23 MM, COMPACT, TBGA-208]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 33 页 / 339 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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S2204  
QUAD GIGABIT ETHERNET DEVICE  
Figure 6 demonstrates the flexibility afforded by the  
S2204. A low jitter reference is provided directly to  
the S2204 at either 1/10 or 1/20 the serial data rate.  
This insures minimum jitter in the synthesized clock  
used for serial data transmission. A system clock  
output at the parallel word rate, TCLKO, is derived  
from the PLL and provided to the upstream circuit as  
a system clock. The frequency of this output is con-  
stant at the parallel word rate, 1/10 the serial data  
rate, regardless of whether the reference is provided  
at 1/10 or 1/20 the serial data rate. This clock can be  
buffered as required without concern about added  
delay. There is no phase requirement between  
TCLKO and TBCx, which is provided back to the  
S2204, other than that they remain within ±3 ns of  
the phase relationship established at reset.  
TRANSMITTER DESCRIPTION  
The transmitter section of the S2204 contains a  
single PLL which is used to generate the serial rate  
transmit clock for all transmitters. Four channels are  
provided with a variety of options regarding input  
clocking and loopback. The transmitters operate at  
1.250 GHz, 10 or 20 times the reference clock fre-  
quency.  
Data Input  
The S2204 has been designed to simplify the paral-  
lel interface data transfer and provides the utmost in  
flexibility regarding clocking of parallel data. The  
S2204 incorporates a unique FIFO structure on both  
the parallel inputs and the parallel outputs which en-  
ables the user to provide a “clean” reference source  
for the PLL and to accept a separate external clock  
which is used exclusively to reliably clock data into  
the device.  
The S2204 also supports the traditional REFCLK  
clocking found in many Gigabit Ethernet applications  
and is illustrated in Figure 7.  
Half Rate Operation  
Data is input to each channel of the S2204 nominally  
as a 10 bit wide word. An input FIFO and a clock  
input, TBCx, are provided for each channel of the  
S2204. The device can operate in two different  
modes. The S2204 can be configured to use either  
the TBCx (TBC MODE) input or the REFCLK input  
(REFCLK MODE). Table 1 provides a summary of  
the input modes for the S2204.  
The S2204 supports full and 1/2 rate operation for all  
modes of operation. When RATE is LOW, the S2204  
serial data rate equals the VCO frequency. When  
RATE is HIGH, the VCO is divided by 2 before being  
provided to the chip. Thus the S2204 can support Gi-  
gabit Ethernet and serial backplane functions at both  
full and 1/2 the VCO rate. See Table 3.  
Operation in the TBC MODE makes it easier for us-  
ers to meet the relatively narrow setup and hold time  
window required by the 125 Mbps 10-bit interface.  
The TBC signal is used to clock the data into an  
internal holding register and the S2204 synchronizes  
its internal data flow to insure stable operation. How-  
ever, regardless of the clock mode, REFCLK is al-  
ways the VCO reference clock. This facilitates the  
provision of a clean reference clock resulting in mini-  
mum jitter on the serial output. The TBC must be  
frequency locked to REFCLK, but may have an arbi-  
trary phase relationship. Adjustment of internal tim-  
ing of the S2204 is performed during reset. Once  
synchronized, the user must insure that the timing of  
the TBC signal does not change by more than ± 3 ns  
relative to the REFCLK.  
Parallel to Serial Conversion  
The 10-bit parallel data handled by the S2204 device  
should be from a DC-balanced encoding scheme, such  
as the 8B/10B transmission code, in which information  
to be transmitted is encoded, 8 bits at a time, into a 10-  
bit transmission character and must be compliant with  
IEEE 802.3z Gigabit Ethernet.  
The 8B/10B transmission code includes serial encod-  
ing and decoding rules, special characters, and error  
control. Information is encoded, 8 bits at a time, into a  
10 bit transmission character. The characters defined  
by this code ensure that short run lengths and enough  
transitions are present in the serial bit stream to make  
clock recovery possible at the receiver. The encoding  
also greatly increases the likelihood of detecting any  
single or multiple errors that might occur during the  
transmission and reception of data1.  
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-  
anced (0,4) 8B/10B Transmission Code," IBM Research Report  
RC9391, May 1982.  
6
October 9, 2000 / Revision E