S2204
QUAD GIGABIT ETHERNET DEVICE
The recommended clocking configuration for exter-
nal clocking mode (REFCLK input clocking) is shown
in Figure 8. TCLKA is sourced from TCLKO, which is
frequency locked to the Reference clock input.
Data Output
Data is output on the DOUT[0:9] outputs. The
COM_DET signal is used to indicate the reception of a
valid K28.5 character.
The S2204 TTL outputs are optimized to drive 65Ω
line impedances. Internal source matching provides
good performance on unterminated lines of reason-
able length.
Figure 8. External Receiver Clocking
REF
OSCILLATOR
Parallel Output Clock Rate
Two output clock modes are supported, as shown in
Table 5. When CMODE is High, a complementary
TTL clock at the data rate is provided on the RBC1/0x
outputs. Data should be clocked on the rising edge of
RBC1x. When CMODE is Low, a complementary TTL
clock at 1/2 the data rate is provided. Data should be
latched on the rising edge of RBC1x and the rising
edge of RBC0x.
REFCLK
TCLKO
PLL
TCLKA
Recovered
Clock
Parallel Data
2
RCxP/N
In Gigabit Ethernet applications, multiple consecu-
tive K28.5 characters cannot be generated. How-
ever, for serial backplane applications this can
occur. The S2204 must be able to operate properly
when multiple K28.5 characters are received. After
the first K28.5 is detected and aligned, the RBC1/0x
clock will operate without glitches or loss of cycles.
Controller/MAC
ASIC/FPGA
SerDes
Table 5. Output Clock Mode (TMODE = 1)
Receiver Output Clocking
Mode
CMODE
RBC1/0x Freq
62.5 MHz
The S2204 parallel output clock source is deter-
mined by the TMODE selection. When REFCLK
clocking is selected (TMODE = Low), the parallel
output clocks (RCxP/N) are sourced from the TCLKA
input. When TCLK clocking is selected (External
Clocking Mode), the parallel output clocks are de-
rived from the recovered clock from each channel.
Table 5A describes the receiver output clocking op-
tions available.
Half Clock Mode
Full Clock Mode
0
1
125 MHz
Table 5A. S2204 Data Clocking
Input Clock
TMODE
Output Clock
Source
Source
When TCLKA is the output clock source, REFCLK
and TCLKA must equal the parallel word rate
(CLKSEL = Low). Additionally, the recovered clocks
and the clock input on TCLKA must be frequency
locked in order to avoid overflow/underflow of the
internal FIFOs. The propagation delay between
TCLKA and DOUTx, listed in Table 21, shows that
the phase delay between TCLKA and the RCxP/N
outputs may vary more than a bit time based on
process variation.
0
1
REFCLK
TBCx
TBCA
RBCx
10
October 9, 2000 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
