S2204
QUAD GIGABIT ETHERNET DEVICE
Table 2. Data to 8B/10B Alphabetic Representation
Data Byte
DIN[0:9] or DOUT[0:9]
0
a
1
b
2
c
3
d
4
e
5
i
6
f
7
g
8
h
9
j
8B/10B Alphanumeric Representation
Reference Clock Input
Serial Data Outputs
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to insure
that the clock recovery units can lock to the serial
data.
The S2204 provides LVPECL level serial outputs.
The serial outputs do not require output pulldown
resistors. Outputs are designed to perform optimally
when AC-coupled.
Transmit FIFO Initialization
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL=1. In both cases the fre-
quency of the parallel word rate output, TCLKO, is
constant at 1/10 the serial data rate. See Table 3.
The transmit FIFO must be initialized after stable
delivery of data and TBC to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. TCLKO will oper-
ate normally regardless of the state of RESET.
Table 3. Operating Rates
REFCLK
Serial
TCLKO
RATE CLKSEL
Frequency Output Rate Frequency
0
0
1
1
0
1
0
1
125 MHz
62.5 MHz
62.5 MHz
31.25 MHz
1250 MHz
1250 MHz
625 MHz
625 MHz
125 MHz
125 MHz
62.5 MHz
62.5 MHz
8
October 9, 2000 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
