QUAD GIGABIT ETHERNET DEVICE
S2204
Table 2 identifies the mapping of the 8B/10B charac-
ters to the data inputs of the S2204. The S2204 will
serialize the parallel data for each channel and will
transmit bit “a” or DIN[0] first.
Table 1. Input Modes
TMODE
Operation
REFCLK MODE. REFCLK used to clock data
into FIFOs for all channels.
Frequency Synthesizer (PLL)
0
1
The S2204 synthesizes a serial transmit clock from the
reference signal. Upon startup, the S2204 will obtain
phase and frequency lock within 2500 bit times after
the start of receiving reference clock inputs. Reliable
locking of the transmit PLL is assured, but a lock-detect
output in NOT provided.
TBC MODE. TBCx used to clock data into
FIFOs for all channels.
1. Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.
Figure 6. DIN Data Clocking with TBC
Figure 7. DIN Clocking with REFCLK
125 MHz
125 MHz or 62.5 MHz
REF
OSCILLATOR
REF
OSCILLATOR
REFCLK
TCLKO
REFCLK
TCLKO
PLL
PLL
DINx[0:9]
DINx[0:9]
TBCx
TBCx
MAC
MAC
S2204
ASIC
ASIC
S2204
7
October 9, 2000 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
