®
DEVICE
SPECIFICATION
QUAD GIGABIT ETHERNET TRANSCEIVER
QUAD GIGABIT ETHERNET TRANSCEIVER
S2066
S2066
FEATURES
• Functionally compliant with IEEE 802.3z Gigabit
Ethernet Applications
• 1250 MHz (Gigabit Ethernet) operating rate
- 1/2 Rate Operation
• Quad Transmitter incorporating phase-locked
loop (PLL) clock synthesis from low speed
reference
• Quad Receiver PLL provides clock and data
recovery
• Internally series terminated TTL outputs
• Low-jitter serial PECL interface
• Local Loopback
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 2.3 W Power dissipation
• Compact 23mm x 23mm 208 TBGA package
GENERAL DESCRIPTION
The S2066 quad transmitter and receiver chip is de-
signed to provide four channels of high-speed serial
data transmission over fiber optic or copper interfaces
conforming to the requirements of the IEEE 802.3z
Gigabit Ethernet specification. The chip runs at
1250.0 Mbit/s serial data rate with an associated 10-
bit parallel data word. The chip provides four separate
transceivers which can be operated individually at
slightly different frequencies.
Each bi-directional channel provides parallel to serial
and serial to parallel conversion, clock generation
and recovery, and framing. The on-chip transmit PLL
synthesizes the high-speed clock from a low-speed
reference. The on-chip quad receive PLL is used for
clock recovery and data re-timing on the four inde-
pendent data inputs. The transmitter and receiver
each support differential PECL-compatible I/O for
copper or fiber optic component interfaces and pro-
vide excellent signal integrity. Local loopback mode
allows for system diagnostics. The chip requires a
3.3V power supply and dissipates approximately 2.3
watts.
Figure 1 shows the use of the S2064 and S2066 in a
Gigabit Ethernet application. Figure 2 summarizes the
input/output signals of the device. Figures 3 and 4
show the transmit and receive block diagrams, re-
spectively.
APPLICATIONS
High-speed data communications
• Ethernet Backbones
• Multi-port Gigabit Ethernet Cards
• Switched networks
• Data broadcast environments
Figure 1. Typical Quad Gigabit Ethernet Application
GE INTERFACE
SERIAL BP DRIVER
MAC
(ASIC)
MAC
QUAD
GIGABIT
ETHERNET
INTERFACE
(ASIC)
TO SERIAL BACKPLANE
S2066
MAC
(ASIC)
S2064
MAC
(ASIC)
October 13, 2000 / Revision C
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
