HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
{ILLTERM} ILLegal TERMination state is entered
when “CR” is received while in the {CONNECTED}
state (i.e., the Destination drops CONNECT while a
valid HIPPI connection exists). This state is exited
when the Source Host drops CNREQ.
{DSTERR} The DeSTination ERRor state is entered
when CON or RDY go active illegally; RDY should
not be active during the {REQ} or {CON1} states,
and neither CON or RDY should be active during
the {ILLTERM} state. While in the {DSTERR} state,
the Source device will report the error by asserting
the SQERR output. The SeQuence ERRor will be
further identified as a DeSTination ERRor by clear-
ing SRNDS to a ‘0’.
{TERMCON} TERMinate CONnection state is entered
when “DR” is received while in the {CONNECTED}
state (i.e., the Source Host drops CNREQ while a
valid HIPPI connection exists). This circuit remains
in this state until the Destination drops CONNECT.
CONNECT SM EXTERNAL OUTPUTS
In addition showing the state transitions resulting from
external inputs to the Source chip, Figure 2 also shows
the external output signals for each defined state.
{ABORT} The ABORT state is entered when “I” or
“DR” are received while a connection is being re-
quested (Source Host drops CNREQ before the
HIPPI connection is established). This state is ex-
ited when the Destination drops CONNECT (if it
was active).
DSTAV DeSTination AVailable signal to the Source
Host. A ‘1’ on this signal indicates the presence of
a functioning Destination on the HIPPI channel. A
‘0’ on this signal indicates the absence of a func-
tioning Destination on the HIPPI channel.
{REJECT} The REJECT state is entered when the
Destination’s response to a connect request results
in more than two (2) but less than 17 consecutive
cycles of “C” (active CON). This state is exited
when the Source Host drops CNREQ.
CNOUT CoNnect OUT signal to the Source Host. This
signal, along with the ACREJ signal (below), indi-
cates the current connection state on the HIPPI
Channel. During a Connect Request, a ‘1’ on this
signal indicates the receipt of a valid response to
the Source (from the Destination) for the Connect
Request. A ‘0’ on this signal, during a Connect Re-
quest, indicates no response (yet) from the Desti-
nation.
{LOSTDEST} The LOST DESTination state is non-
operational, and is entered when the HIPPI Inter-
connect Destination-to-Source signal goes inactive
during any of the operational states. This circuit
remains in this state until the Source Host system
forces a RESET or a WAIT mode (MSEL2-0 in-
puts).
After a connection is accepted, this signal shall be
the same state as CONNECT on the HIPPI chan-
nel, and therefore will indicate to the Source Host
an illegal termination (termination initiated by the
Destination), or the acknowledgment by the Desti-
nation of a normal termination.
{NODEST} The NO DESTination state is non-opera-
tional, and is entered anytime there is no Destina-
tion-to-Source Interconnect signal while the Source
Host is forcing a RESET or WAIT mode via the
MSEL2-0 inputs. This state is exited only by “RST”
(the HIPPI Interconnect Destination-to-Source sig-
nal going active while still in the RESET or WAIT
mode).
ACREJ ACcept/REJect signal to the Source Host. This
signal, along with the CNOUT signal (above), indi-
cates the Destination’s response to the Source’s
Connect Request. A ‘1’ on this signal when CNOUT
goes active during a Connect Request indicates an
ACCEPTed connection. A ‘0’ on this signal when
CNOUT goes active during a Connect Request in-
dicates a REJECTed connection.
{SRCERR} The SouRCe ERRor state is entered when
CNREQ goes active illegally. This is possible dur-
ing the {ABORT} and {TERMCON} states, where
this circuit is waiting for the channel to go idle after
a Source initiated termination. While in this state,
the Source device will report the error by asserting
the SQERR output. The SeQuence ERRor will be
further identified as a SouRCe ERRor by setting
SRNDS to a ‘1’.
2.0 S2020 HIPPI DATA/FIFO CONTROL
The HIPPI Source device Host Data/FIFO State Ma-
chine (SM) is part of the Host Data/FIFO Control Block.
The State Machine controls the flow of data and status
from the Source Host FIFO to the S2020 Source de-
vice. The Data/FIFO SM also controls the generation of
the HIPPI channel control signals to properly delimit the
data and respond to the data transfer commands of the
Source Host system.
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