HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
The Host Data/FIFO SM has inputs from the Source
Host system, the Connect Control State Machine and
the internal Flow control circuit. Based on the current
set of inputs and the last state of this state machine, the
next Data/FIFO state is entered and a related set of
outputs is generated to the Source Host and to the
HIPPI channel.
DATAV DATa AVailable signal from the Source Host:
Indicates the availability of at least one more data
word, or I-Field in the Source Host FIFO. A ‘1’ on
this signal will enable the Source device to advance
any pending operation that requires more data from
the Host. A ‘0’ on this signal will prevent the ad-
vancement of any such operations, and will legally
terminate the current data Burst being transferred
across the HIPPI channel.
As before, all external device signal names shall be
CAPITALIZED and underlined, the SM input ‘alphabet’
or decode names shall be in double quotes (“), and all
internal state names shall be enclosed in curly brackets
‘{}’. Signals internal to the Source device other than
previously defined state names shall be in caret brack-
ets ‘< >’.
Internal Inputs
<FLOWON> Flow control signal from the READY/
BURST counter block: Indicates the current capac-
ity of the HIPPI channel (Destination) to accept a
HIPPI Burst. A ‘1’ on this signal enables the trans-
mission of one Burst to be initiated, if available from
the Source Host system. A ‘0’ on this signal allows
the completion of any Burst that has been initiated,
but disables any subsequent Bursts. The state of
this signal is observable at the DTREQ (DaTa
REQuest) output of the Source Device.
HOST DATA/FIFO SM INPUTS
External Inputs
PKTAV PacKeT AVailable signal from the Source
Host: Indicates the current delimiting of data across
the HIPPI channel. A ‘1’ on this signal indicates the
Source Host’s request to either initiate a Packet or
maintain the current Packet on the HIPPI channel.
A ‘0’ on this signal indicates the Source Host’s re-
quest to terminate the current Packet.
<CONREQ> Connect request signal from the Connect
Control State Machine: This signal is active for any
of the Connect SM states {REQ} thru {CON16} dur-
ing a normal HIPPI channel Connection Request se-
quence. When active, this signal allows the Data/
FIFO SM to read the I-Field from the Source Host
FIFO, and then present the I-Field data and the REQ
signal to the HIPPI channel.
BSTAV BurST AVailable signal from the Source Host:
Indicates the availability of other controls and data
from the Source Host system. A ‘1’ on this signal
will enable the Source device to initiate a new read
sequence from the Source Host FIFO. A ‘0’ will
disable the initiation of any new read sequences.
This signal must not go active until at least one
valid HIPPI Burst is available from the Source Host.
If this signal goes inactive after a Burst read se-
quence has begun, the current burst will be com-
pletely read, but subsequent read operations will be
disabled.
<CNNECTED> Connected signal from the Connect
Control State Machine: This signal is active only for
the {CONNECTED} state. A ‘1’ on this signal en-
ables all the HIPPI data delimiting and transfer
functions. A ‘0’ will disable all delimiting and trans-
fer functions.
<256THWRD> The Terminal Count signal from the 8-
bit word counter of the Host Data/FIFO Control
Block: This signal indicates that the 256th word of
the current Burst is being transferred from the FIFO
to the Source device. A ‘1’ on this signal will legally
terminate the current Burst. A ‘0’ will allow the
Source device to transfer at least one more data
word.
SHBST SHort BurST signal from the Source Host:
Indicates the end of a HIPPI data Burst with a
length shorter than 256 words. A ‘1’ on this signal
during an active Packet will terminate the current
burst with the current word being the last word of
the burst, and will initiate the completion and sub-
sequent transmission of the LLRC word. A ‘0’ on
this signal will allow the Source device to transfer at
least one more data word from the Source Host
FIFO to the HIPPI channel unless the current word
is the 256th word of the current Burst.
<RESET> The Reset signal from the Clock Control
Block: This signal is the registered decode of the
MSEL2-1 for the Mode = 0 state. A ‘1’ on this signal
indicates the Reset state for the entire Source de-
vice including the Host Data/FIFO SM. A ‘0’ on this
signal will enable all other inputs to the SM.
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