HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
{LLRC} The LLRC state is entered after the {LSTWD}
DATA/FIFO SM EXTERNAL OUTPUTS
state. This state will deassert the BST signal on the
HIPPI channel while completing and posting the
LLRC word to the channel. If the current Packet
has been terminated by the Source Host system
(PKTAV was deasserted at the read of the last
word of the Burst), then the {IDLE} state will be
entered. If the “DRDY” decode is true (BSTAV and
DATAV are both asserted), and the current Packet
is to be continued, then the {WTBST} state is en-
tered. If the current Packet is to be continued, but
the “DRDY” decode is false, then this state is main-
tained. No read operations are performed in this
state.
REQ REQuest signal to the HIPPI channel. The func-
tions of this signal are defined in the HIPPI-PH
spec.
BRST BuRST signal to the HIPPI channel. The func-
tions of this signal are defined in the HIPPI-PH
spec.
PKT PacKeT signal to the HIPPI channel. The func-
tions of this signal are defined in the HIPPI-PH
spec.
NREN Not Read ENable signal to the Source Host
system FIFO. This is an active low signal to be
used to enable the FIFO to load a new data word
into its output register. This signal is controlled not
only by the state of the Data/FIFO SM, but also by
the inputs PKTAV, SHBST, DATAV and BSTAV.
{WTBST} The WaiT BurST state is entered after one
Burst is complete and the “DRDY” decode is true.
One read operation is performed in this state. If
PKTAV is asserted at that read operation, then the
{PENDBST} state is entered. If PKTAV was
deasserted at the read, then the {IDLE} state is
entered.
As an example, in the {RDIFL} state, the detection
of the “IFLD” decode (PKTAV =’0', SHBST = ‘1’)
will asynchronously deassert (raise to logical ‘1’)
the NREN signal prior to the next rising edge of
RDCLK such that the tagged data remains held in
the FIFO’s output buffer. Similarly, the “DRDY” de-
code asynchronously controls the assertion of
NREN on the transition from the trapped {IDLE}
state to the {WAITPKT} state.
{SRCERR} The SouRCe ERRor state is entered if the
PKTAV changes from a “1” to a “0” and the “FLOF”
decode is false during the {PNDBST} state.
This state is exited to the {INIT} state when the
HIPPI Connection is broken or if the <RESET> sig-
nal is true. The state is exited to the {DSTERR}
state if the “CNRQ” decode is true. This error state
is reported to the Source Host system by setting
both SQERR and SRNDS output to logical “1”.
{DSTERR} The DeSTination ERRor state is entered if
the <CONREQ> signal is received while a valid
HIPPI Connection is already established. The most
likely cause of this error is an unstable signal on the
HIPPI channel from the Destination. This state is
also entered if CON is asserted when not expected
(during the {INIT} or {RDIFL} states). This state is
exited by either the “RST” or “DSCN” decodes be-
ing true, either of which force the {INIT} state. This
error state is reported to the Source Host system by
setting the SQERR output to “1” and the SRNDS
output to “0”.
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