HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
The S2020 sets the PACKET signal on the HIPPI Chan-
nel prior to setting the BURST signal as required by the
HIPPI Standard. If the external DTREQ signal is low
(Burst and Ready counters are equal), there are no “un-
answered” READYs. In this case the S2020 will pause in
the {PENDBST} state until a READY signal is detected
and the Ready counter is incremented.
son between the Ready Counter and the Last Burst
Register is used to prevent the Ready Counter from
being incremented to a value greater than the old Burst
Count. Thus the Ready Counter is prevented from
“wrapping around” after receiving more than 65,535 un-
answered READY signals from the Destination.
The 65,536th and subsequent READY signals will be
disregarded until at least one more Burst is completed,
the Burst Counter incremented, the Last Burst Register
updated, and the comparator conditions re-enable the
incrementing of the Ready Counter.
This function allows the Destination to “meter” the trans-
mission of HIPPI Bursts on a one-by-one basis. A logic
high on the DTREQ signal indicates that the S2020 is
allowed to proceed, setting the BURST signal active
and reading the next word of the Burst from the FIFO.
If the Host decides to terminate the Packet while in the
inter-Burst state, a single word must be loaded in the
FIFO with the accompanying PKTAV bit set to 0. While
the data at the inputs of the S2020 will appear at the
HIPPI Channel outputs, the inactive BURST signal will
cause the Destination to ignore that data. The low
PKTAV read from the FIFO will again vector the S2020
to the inter-packet {IDLE} state.
While this process when started proceeds automati-
cally, the Host system can observe its progress via the
DTREQ output.
The BSTAV should not be placed in the FIFO as a
data bit, since it is used along with the DATAV signal
to start and stop transmission gracefully at even Burst
boundaries.
After the last Packet of the transmission is completed,
the Source Host may terminate the connection by plac-
ing a logic low on the CNREQ input. The S2020 will
deassert the REQUEST signal on the HIPPI Channel,
enter the {TERMCON} state and remain there until the
Destination deasserts the CONNECT signal. At that point
the {IDLE} state will be re-entered.
In all cases the BSTAV must be synchronized with the
25 MHz RDCLK for reliable operation of the S2020. The
rising edge of BSTAV asynchronously controls the lead-
ing edge of the low active NREN signal.
Once the Connection is established and the first Packet
and Burst are started, the S2020 Source Device will
generate properly formatted Bursts with the appropriate
LLRC word and inter-burst idle cycles as long as the
FIFO has data and the PKTAV and BSTAV signals
remain high. The BSTAV signal is used to pause at the
even 256 word Burst boundaries while the Host System
“refills” the FIFO.
As an alternative, the Host may issue a Mode 0 Reset
command to terminate the Connection. The REQUEST
signal will similarly be deasserted and the {INIT} state
will be entered until the Destination deasserts CON-
NECT and the Host System deasserts CNREQ. It is
recommended that the first method be used for graceful
termination since the path through the {TERMCON}
state allows the Host to monitor the CONNECT signal
status via the CNOUT output.
The BSTAV signal must be set for at least the first word
of the Burst. Once started the Burst will continue until
256 words are transmitted unless the SHBST signal is
set active, the PKTAV signal is set inactive, or the
DATAV signal is set low inactive. The word being read
from the FIFO at the time that any one of these three
events occurs becomes the last word of the Burst. The
last word is transmitted, followed immediately by the
LLRC for that Burst, and the S2020 pauses and waits
for both the DATAV and BSTAV to be true (active high).
The HIPPI Source device connect control State Ma-
chine (SM) controls the Connection state of the HIPPI
channel to which it is attached. The Connect Control
SM has inputs from the Source Host and form the
HIPPI channel (remote Destination). Based on the cur-
rent set of inputs and the last state of this circuit, the
next Connect state is entered and a related set of out-
puts is generated to the Source Host and to the HIPPI
channel (remote Destination).
If the Burst was terminated due to an inactive PKTAV,
the S2020 will wait for DATAV and BSTAV in the internal
inter-packet {IDLE} state. Inter Burst pauses within a
Packet cause the S2020 to wait in the {LLRC} state.
For this discussion all external device signal names
shall be CAPITALIZED and underlined, the SM input
‘alphabet’ or decode names shall be in double quotes
(“), and all internal state names shall be enclosed in
curly brackets ‘{}’.
Each time a Burst reaches the last word condition, the
Burst Counter is incremented and the previous value of
the Burst Counter is saved in an internal Last Burst
Register. In addition to the comparison between the
Ready Counter and the Burst Counter used to control
the FLOWON and DTREQ signals, a second compari-
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