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APPLICATION NOTE
HIPPI
HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
BiCMOS PECL CLOCK GENERATOR
S2020/S2021 SOURCE DEVICE STATE MACHINES
Sharp all share this feature. Even if the external data
source memory had “correct” parity available at the in-
puts of the S2020, the two clock period parity error
would be observed.
S2020 HIPPI SOURCE CONNECT CONTROL
The S2020 Source Device meets the signalling protocol
for the Hippi-Source as determined by ANSI X3.183-
1991 HiPPI-PH Mechanical Electrical and Signalling
Protocol Specification. As the Source, the S2020 func-
tions as the initiator and controller of all data transfers
on the Hippi channel.
The first function that must be performed after the
power-up initialization of the S2020 (RESET Mode 0) is
to determine the status of the Destination to Source
Interconnect [DSIC] signal. That signal, generated by
the remote HIPPI Destination, is an input signal from
the HIPPI Channel to the S2020 and must be in the
logic low (active) state for any control or data transfer
functions to be valid on the HIPPI Channel.
The RESET Command (Mode 0) initializes all internal
state machines in the S2020 and clears all data and
parity bit registers to zero. The only function that is not
cleared or held at an initialized state is the clock control
which generates the internal 25 MHz and the external
RDCLK signal. The RESET Command provides phase
control of the internal and external clocks.
The filtered and inverted state of the DSIC input is avail-
able at the Destination Available [DSTAV] output. Since
the S2020 has the capability of switching its own
Source to Destination output signal to the inactive state
during Reset and Board Test modes, the Device must
be placed in the Wait for Destination mode (Mode 2)
immediately after RESET to allow the filter to recognize
either the static low (active) DSIC input or the high to
low transition of the DSIC input.
If the RESET Command is placed on the MODE(2:0)
inputs while the RDCLK output is in the logic high state,
there will be no change in the continuous 25 MHz signal
observed at the RDCLK output. If, however, the RESET
Command is placed on the MODE(2:0) inputs while the
RDCLK output is in the logic low state, the RDCLK
output will go high after the next rising edge of the 50
MHz input, remain high for two cycles of the 50 MHz
input and then produce a rising edge on the third 50
MHz falling edge applied to the S2020. From that point
until the next application of the RESET Command the
RDCLK (and the internal clocks) will be a continuous 25
MHz signal synchronized to the 50MHZ input rising
edge.
If the S2020 is placed directly from the RESET Mode
into the Operational Mode (Mode 3), the DSTAV output
will not correctly respond to the DSIC input state, even
if the DSIC input is already in the active low condition
when the RESET to Operational mode change is made.
The Wait for Destination mode avoids possible control
ambiguities in systems where both Source and Destina-
tion have active control of their respective Interconnect
signals.
This “phase slip on low” function can be used to unam-
biguously set the phase relation between the 50 MHz
input and the RDCLK output. Since most of the Host
interface control inputs are required to be synchronous
with the 25 Mhz RDCLK output, this phase slip control
gives the user the capability of aligning the S2020’s
timing to the 50 MHz and 25 MHz used in the external
Host circuitry.
With the S2020 in the Wait for Destination mode (Mode
2), the observation of an active high state on the
DSTAV output indicates that the internal reset and ini-
tialization cycle of the entire HIPPI Channel (both
Source and Destination) is complete. The S2020 may
now be legally placed in the Operational mode, and the
internal Connect State Machine of the S2020 will be
placed in the {IDLE} state.
It should be noted that while the RESET Command
clears the Parity Error bit (INPRR output), the internal
data and parity registers have also been cleared. This
“zero data/zero parity” condition is a Parity Error with
respect to the HIPPI odd byte parity convention. If a
parity correct word is present at the inputs of the S2020
at the time the RESET state is exited, there will be a
two clock period parity error bit on the INPRR output. If
the attached FIFO has also been cleared during the
RESET Command, the INPRR bit will remain high until
three clocks after the first read cycle of the FIFO.
If there is any interruption of the DSIC input greater
than the filter integration time (four clock cycles), the
Connect State Machine will be forced to the
{LOSTDEST} state. This will immediately stop any cur-
rent data transfer, and cause the REQUEST, PACKET
and BURST signals on the HIPPI Channel to go to the
inactive state. The DSTAV signal will go low to indicate
this condition to the Source Host System. The only re-
covery from this condition is the RESET and WAIT se-
quence described above. It is the responsibility of the
Source Host System to exercise a reasonable “time-
out” if the remote Destination does not generate a
stable active low state on the DSIC signal.
While there are some differences in FIFO or “FIFO
equivalent” memory structures that have been success-
fully used with the S2020, the available or announced
synchronous clocked FIFOs from IDT, Cypress and
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