HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
The S2020 distinguishes between Connect Accept and
Connect Reject conditions in accordance with the
HIPPI Specification. If the CONNECT signal from the
HIPPI Channel is detected for less than four clock
cycles (160 nsec) it is ignored and the S2020 remains
in the {REQ} state.
Once the DSTAV signal is observed at an active high
state and the Operational Mode (Mode 3) is com-
manded, the S2020 is ready to initiate a Connection
Request sequence. The design of the S2020 is opti-
mized to use the external synchronous FIFO as the
source of the I-Field Word as well as the PKTAV and
SHBST signals used to flag the I-Field Word. If the I-
Field and/or the two control signals are not placed in the
FIFO, care must be taken that their timing is controlled
to meet the specification of the Data Sheet. Failure to
honor that timing will cause erroneous and unpredict-
able operation of the FIFO with resultant data loss.
If the CONNECT signal is detected for more than three
and less than twenty clock cycles with no activity de-
tected on the READY signal, The Destination is judged
to have issued an active Connect Rejection. In that
case the S2020 will place a logic high on the CNOUT
output and a logic low on the ACREJ output. This con-
dition will persist until the Host returns the CNREQ
signal to the low state or the Host executes the Mode 0
Reset sequence.
The S2020 acts as a continuously running, two register
deep pipeline. In the HIPPI application, the only point at
which a data word is held static for multiple clock cycles
is the output register of the FIFO. The NREN output of
the S2020 is applied to the Not Read Enable input of
the FIFO to control this register.
The READY signal is also monitored to determine the
Connect Accept or Connect Reject status. If the
READY signal is detected two or more clock cycles
after the detection of CONNECT signal, the Connec-
tion is considered as accepted and the 11 pattern is
posted to the CNOUT and ACREJ outputs. If the Desti-
nation drops the CONNECT signal at this point while
the CONREQ input remains high, the {DESTERR}
state is entered.
It should be also noted that for the recommended FIFO
and most equivalents, the operation of writing into the
FIFO from the Host System does not directly write any
data into the FIFO’s output register. The data in the
output register is indeterminate (it may be zero if the
entire system including the FIFO was initialized, other-
wise it is usually the last transmitted data word.)
If a READY signal is detected during the Connect Re-
quest cycle or later at any time while in the {CON-
NECTED} state, the Ready counter in the S2020 will
be incremented by one. This counter and a similar
Burst counter (incremented at the last word of every
Burst) are compared to generate, when not equal, the
external DTREQ signal. This inequality is also used
internally by the S2020 to automatically control the flow
of Bursts in response to received READYs. Both
counters are cleared to zero at Reset Mode or at the
termination of the current {CONNECTED} state.
Placing the I-Field and the two signals defining the I-
Field in the FIFO eliminates any ambiguity as to the
previous contents or state of the FIFO. If the FIFO has
been filled with data, and the Not Empty output of the
FIFO is connected to the DATAV input of the S2020,
then a high signal on the CNREQ input and the high
signal already at the DATAV input will cause an active
low on the NREN output. The NREN signal will remain
low for at least one cycle of the 25 MHz RDCLK until
the 01 condition is observed on the PKTAV and SHBST
inputs respectively.
If the I-Field is to be sourced from a register separate
from the FIFO, the NREN signal must be blocked to
avoid erroneously advancing the FIFO.
The detection of the 01 condition will asynchronously
raise the NREN signal to the inactive state, locking the
current data word (assumed by its PKTAV/SHBST label
to be the I-Field) in the output register of the FIFO. Two
clock cycles later, this data is available at the HIPPI
Channel outputs and the REQUEST signal is asserted
on the HIPPI Channel.
Care must also be taken to control the FIFO in order to
recognize the beginning of the Burst data if the PKTAV
and SHBST are not used to delimit the data.
Once the Connection is established, the S2020 waits
in the {IDLE} state until both BSTAV and DATAV input
signals are asserted before starting any further data
transfers. The BSTAV is used to initiate the search of
the FIFO for the first word of the Burst and Packet. It
should be noted that the BSTAV signal must be set
high before the S2020 can attempt to read in the
PKTAV signal.
The REQUEST signal will remain active on the HIPPI
Channel until the CNREQ input is returned to the logic
low state. The S2020 will make no more read requests
of the FIFO until the Destination has responded with a
Connect Accept or a Connect Reject. This status is
indicated by the CNOUT and ACREJ signals. If both of
these outputs are at logic high, the Connection has
been accepted and recognized at both Source and
Destination.
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