HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
If the process that empties the FIFO is faster than the
data rate of the HIPPI Channel, the RDYIN input may
be driven by a free-running TTL signal at a frequency
less than or equal to 12.5 MHz. In that configuration the
Buffer counter will quickly fill to 65,535.
S2021 HIPPI DESTINATION CONNECT
CONTROL
S2021 HIPPI Destination Device Normal
Functional Sequence
After a connection is accepted, the READY signals are
continuously generated at the maximum rate allowed
by the HIPPI Standard (160 ns asserted, 160 ns
deasserted) and counted in the internal READY
Counter until the two counters are equal. If a continu-
ous toggling signal is applied to RDYIN, 65,535 READY
pulses will be sent at the maximum rate. From that
point on each received Burst will allow one and only
one READY pulse to be generated.
The S2021 Destination Device responds to Connection
and data transfer requests received from the HIPPI
Source.
The RESET Command (Mode 0) initializes all internal
registers and state machines of the S2021. The Reset
Command also places all Host side TTL outputs in the
high-impedance state and the HIPPI Channel outputs
(CONNECT and READY) in the deasserted state. The
Destination to Source Interconnect output (DSIC) is
also placed in the high logic low state. If the circuit
recommended on page 19 of the S2020/S2021 Device
Specification is used, this will result in a high inactive
level on the HIPPI Channel DSIC signal.
When an active REQUEST is detected on the HIPPI
Channel the {REQCON} state and the {IFIELD} state
are entered. The data on the HIPPI Channel is pre-
sented at the outputs of the S2021 along with a logic
high on the CONRQ output.
After the RESET Command initialization is complete the
Device should be placed in the operational state through
the Mode 5 Command. The Host system should place a
logic low signal on the CONIN input. The SRCAV output
should then be monitored to determine the status of the
Source Driving the HIPPI Channel.
The SELB outputs assume the 001 code for the HIPPI
I-Field. At this point the Host system must decide to
either accept or reject the connection. The Host system
must place a logic high on the CONIN input while hold-
ing the ACCRJ at logic high to accept the connection. If
ACCRJ is held low when CONIN is asserted the con-
nection will be rejected. For applications where all
REQUESTs must be accepted, the CONRQ output
may be connected directly to the CONIN input and the
ACCRJ input held high.
If this signal is at a logic 0, either the Source to Destina-
tion Interconnect (SDIC) is inactive or one of the Chan-
nel Control signals (REQUEST, PACKET or BURST)
from the Source is active. A logic 1 on the SRCAV
output indicates the presence of a functional Source
capable of initiating data transfers.
If the REQUEST is rejected (CONIN =1, ACCRJ =0)
the S2021 will assert the CONNECT signal on the
HIPPI Channel for four clock cycles and then deassert
the CONNECT signal for four cycles. If at the end of this
sequence the Source has deasseted the REQUEST
signal the S2021 will return to either the {IDLDSAB}
state (CONIN=1) or the {IDLENAB} state (CONIN=0).
When the {IDLENAB} state is reached the S2021 is
able to process another Connection Request from the
Source.
In the initialized but not connected condition, the S2021
cycles through the {DISCON0-2} state sequence. This
is monitored by the host system by observing the 5,6,7
repeating sequence on the SELB(2:0) outputs and the
appropriate internal status words on the data outputs.
At this point the Host system may initialize the internal
Buffer Counter of the S2021 with the number of Burst-
sized (256 word) buffer blocks available in the external
FIFO and memory system. This is accomplished by
placing a rising edge signal on the RDYIN input for
each buffer block to be counted. Thus, if the available
FIFO is 4K words deep, and the process that empties
the FIFO is slower than the data rate of the HIPPI
Channel, 16 pulses would be supplied to the RDYIN
input.
If the Host system has accepted the connection request
(CONIN=1, ACCRJ=1) the S2021 will return to the
{DISCON0-2} sequence until the CONNECT signal has
been asserted for four clock cycles. At that point the
S2021 enters the {IDLE} state (SELB=3) and remains
there until the Source asserts the PACKET signal on
the HIPPI Channel.
During the disconnected condition, the state of the
Buffer counter can be monitored by observing its con-
tents in the lower half of the Flow status Word 2 which
is presented to the outputs during the SELB=7 state.
The Buffer Counter has a capacity of 2exp16 - 1 counts
(65,535 buffers). Inputs to RDYIN greater than this will
be ignored.
When the PACKET signal is detected from the Chan-
nel, the S2021 responds by placing a logic 1 on the
PKOUT output and waits for a Burst data transfer to
begin. The SELB bus remains in state 3. If the Source
drops the PACKET on the Channel without beginning a
Burst, i.e. attempts to form an “empty” Packet, the
S2021 will detect a Sequence Error.
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