1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
S2009
OTHER OPERATING MODES
Operating Frequency Range
JTAG TESTING
The JTAG implementation for the S2009 is compli-
ant with the IEEE1149.1 requirements. JTAG is used
to test the connectivity of the pins on the chip. The
Test Access Port (TAP) provides access to the test
logic of the chip. When Test Reset (TRS) is asserted
the TAP is initialized. TAP is a state machine that is
controlled by Test Mode Select (TMS). The test in-
struction and data are loaded through Test Data In
(TDI) on the rising edge of Test Clock (TCK). When
TMS is High, the test instruction is loaded into the
instruction register. When TMS is Low, the test data
is loaded into the data register. Test Data Out (TDO)
changes on the falling edge of TCK. All input pins,
including clocks, that have boundary scan are ob-
serve only. They can be sampled in either normal
operational or test mode. All output pins that have
boundary scan, are observe and control. They can
be sampled as they are driven out of the chip in
normal operational mode, and they can be driven out
of the chip in test mode using the Extest instruction.
Since JTAG testing operates only on digital signals
there are some pins with analog signals that JTAG
does not cover. The JTAG implementation has the
three required instruction, Bypass, Extest, and
Sample/Preload.
The S2009 is designed to operate at serial baud
rates of 1.3 to 1.6 GHz (1.04 – 1.28 Gbps user data
rate).
Loopback Mode
When loopback mode is enabled, the serial data
from the transmitter is provided to the serial input of
the receiver, as shown in Figure 9. This provides the
ability to perform system diagnostics and off-line
testing of the interface to verify the integrity of the
serial channel. Loopback mode is enabled indepen-
dently for each channel using its respective
Loopback Enable input (LPENx).
When squelch is enabled, the transmitter output
driver is powered down. The serial outputs (TXP and
TXN) will be held at a logic High state due to source
followers, which in turn makes the differential state,
TXP minus TXN, indeterminate. Squelch is enabled
independently for each channel using its respective
Squelch input (SQLx_N).
TEST MODES
The S2009 has a testability input to aid in functional
testing of the device. The test mode is entered when
CH_LOCK is High and TCLKB is High. Thus users
must take care to insure that TCLKB is held Low
when operating in Channel Lock Mode.
JTAG Instruction Description:
The BYPASS register contains a single shift-register
stage and is used to provide a minimum-length serial path
between the TDI and TDO pins of a component when no
test operation of that component is required. This allows
more rapid movement of test data to and from other com-
ponents on a board that are required to perform test op-
erations.
Figure 9. S2009 Diagnostic Loopback Operation
The EXTEST instruction allows testing of off-chip circuitry
and board level interconnections. Data would typically be
loaded onto the latched parallel outputs of boundary-scan
shift-register stages using the SAMPLE/PRELOAD in-
struction prior to selection of the EXTEST instruction.
CSU
CRU
The SAMPLE/PRELOAD instruction allows a snapshot of
the normal operation of the component to be taken and
examined. It also allows data values to be loaded onto the
latched parallel outputs of the boundary-scan shift register
prior to selection of the other boundary-scan test instruc-
tions.
Notes:
1. Serial output data remains active during loopback operation to
enable other system tests to be performed.
2. Serial output data will become inactive during squelch operation
The IDCODE instruction allows selection of the de-
vice identification register to be connected for serial
access between Test Data Input (TDI) and Test Data
Output (TDO). When the IDCODE instruction of the
device is selected, all test data registers perform
their system function.
17
February 9, 2001 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
