S2004 – Quad Serial Backplane Device
Revision J – April 7, 2006
Data Sheet
TRANSMITTER DESCRIPTION
The transmitter section of the S2004 contains a single
PLL which is used to generate the serial rate transmit
clock for all transmitters. Four channels are provided
with a variety of options regarding input clocking and
loopback. The transmitters can operate in the range of
.98 GHz to 1.3 GHz, 10 or 20 times the reference
clock frequency. The transmitter can also operate from
0.49 GHz to 0.65 GHz in the half rate operation mode.
Data Input
The S2004 has been designed to simplify the parallel
interface data transfer and provides the utmost in flexi-
bility regarding clocking of parallel data. The S2004
incorporates a unique FIFO structure on both the par-
allel inputs and the parallel outputs which enables the
user to provide a “clean” reference source for the PLL
and to accept a separate external clock which is used
exclusively to reliably clock data into the device. Data
can also be clocked in using the REFCLK.
Data is input to each channel of the S2004 nominally
as a 10 bit wide word. This consists of eight data bits
of user data, KGEN, and DN. An input FIFO and a
clock input, TCLKx, are provided for each channel of
the S2004. The device can operate in two different
modes. In CHANNEL-LOCKED mode all four bytes of
input data are clocked into their respective FIFOs
using a common clock. The S2004 can be configured
to use either the TCLKA (TCLK MODE) input or the
REFCLK input (REFCLK MODE). In NORMAL mode,
each byte of data is clocked into its FIFO with the
TCLKx provided with each byte. Table 1 provides a
summary of the input modes for the S2004.
Table 1. Input Modes
CHANLOCK
0
0
1
1
TMODE
0
1
0
1
Operation
NORMAL REFCLK MODE. REFCLK used to clock data into FIFOs for all channels. (No receiver
byte de-skew.)
NORMAL TCLK MODE. TCLKx used to clock data into FIFOs for all channels. (No receiver byte
de-skew.)
CHANNEL LOCK MODE. REFCLK MODE. REFCLK used to clock data into FIFOs for all chan-
nels. (Receiver byte de-skew active.)
CHANNEL LOCK MODE. TCLKA MODE. TCLKA used to clock data into FIFOs for all channels.
(Receiver byte de-skew active.)
Operation in the TCLK MODE makes it easier for
users to meet the relatively narrow setup and hold
time window required by the parallel 10-bit interface.
The TCLK signal is used to clock the data into an inter-
nal holding register and the S2004 synchronizes its
internal data flow to insure stable operation. However,
regardless of the clock mode, REFCLK is al-ways the
VCO reference clock. This facilitates the provision of a
clean reference clock resulting in minimum jitter on the
serial output. The TCLK must be frequency locked to
REFCLK, but may have an arbitrary phase relation-
ship. Adjustment of internal timing of the S2004 is
performed during reset. Once synchronized, the user
must insure that the timing of the TCLK signal does
not change by more than ± 3 ns relative to the REF-
CLK.
S2004. A low jitter reference is provided directly to the
S2004 at either 1/10 or 1/20 the serial data rate. This
insures minimum jitter in the synthesized clock used
for serial data transmission. A system clock output at
the parallel word rate, TCLKO, is derived from the PLL
and provided to the upstream circuit as a system
clock. The frequency of this output is constant at the
parallel word rate, 1/10 the serial data rate, regardless
of whether the reference is provided at 1/10 or 1/20
the serial data rate. This clock can be buffered as
required without concern about added delay. There is
no phase requirement between TCLKO and TCLKx,
which is provided back to the S2004, other than that
they remain within ± 3ns of the phase relationship
established at reset.
1. Note that internal synchronization of FIFOs is performed upon de-assertion of RESET or when the synchronization pattern is generated
(SYNC = 1 DNx = 1).
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
