Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Figure 5. Receiver Block Diagram
TMODE
CMODE
RATE
REFCLK
EOFA
TXABP
8B/10B
KFLAGA
ERRA
Decode
Framing
Data
Stretching
Timing
FIFO
DOUT CRU
Serial-
Parallel
8
10
(output)
8
Q
RXAP
RXAN
DOUTA[0:7]
RCAP/N
2
LPENA
TXBBP
EOFB
KFLAGB
ERRB
8B/10B
Decode
Framing
Data
Stretching
Timing
FIFO
(output)
DOUT CRU
Serial-
Parallel
8
10
8
RXBP
RXBN
DOUTB[0:7]
RCBP/N
2
LPENB
TXCBP
EOFC
KFLAGC
ERRC
8B/10B
Decode
Framing
Data
Stretching
Timing
FIFO
(output)
DOUT CRU
Serial-
Parallel
10
8
8
2
RXCP
RXCN
DOUTC[0:7]
RCCP/N
LPENC
TXDBP
EOFD
KFLAGD
ERRD
8B/10B
Decode
Framing
Data
Stretching
Timing
FIFO
(output)
DOUT CRU
Serial-
Parallel
8
10
8
RXDP
RXDN
DOUTD[0:7]
2
RCDP/N
LPEND
CH_LOCK
8
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