Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Figure 3. S2004 Input/Output Diagram
TRS
TMS
TCK
TDI
TDO
RESET
RATE
REFCLK
CLKSEL
TMODE
TX AP /N
TXB P/N
TX CP /N
TCLK O
SYNC
DINA[0:7]
DNA, KGENA
10
TCLK A
DINB[0:7]
DNB, KGENB
10
TCLK B
DINC[0:7]
DNC, KGENC
10
TX DP /N
RXAP/N
RXBP/N
RXCP/N
RXDP/N
TCLK C
DIND[0:7]
DND, KGEND
10
TCLK D
ERRA
DOUTA[0:7]
EOFA, KFLAGA
10
RCA P/N
ERRB
DOUTB[0:7]
EOFB, KFLAGB
10
RCB P/N
ERRC
DOUTC[0:7]
EOFC, KFLAGC
10
RCC P/N
ERRD
DOUTD[0:7]
EOFD, KFLAGD
10
RCD P/N
LPENA
LPENB
LPENC
CH_LOCK
CMODE
LPEND
6
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
