Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Table 4. Data to 8B/10B Alphabetic Representation
Data Byte
DIN[0:9] or DOUT[0:9]
0
1
b
2
c
3
d
4
e
5
i
6
f
7
g
8
h
9
j
8B/10B Alphanumeric Representation
a
Reference Clock Input
The frequency of the reference clock must be either 1/
10 the serial data rate, CLKSEL = 0, or 1/20 the serial
data rate, CLKSEL = 1. In both cases the frequency of
the parallel word rate output, TCLKO, is constant at 1/
10 the serial data rate. See Table 5.
The reference clock input must be supplied with a low-
jitter clock source. All reference clocks in a system
must be within 200 ppm of each other to insure that
the clock recovery units can lock to the serial data.
Table 5. Operating Rates
RATE
CLKSEL
REFCLK Frequency
SDR/10
Serial Output Rate
0.98-1.3 GHz
TCLKO Frequency
SDR/10
0
0
1
0
1
0
SDR/20
0.98-1.3 GHz
SDR/10
1
SDR/10
0.49-0.65 GHz
0.49-0.65 GHz
SDR/10
1
SDR/20
SDR/10
Note: SDR = Serial Data Rate.
Serial Data Outputs
Test Functions
The S2004 provides LVPECL level serial outputs. The
serial outputs do not require output pulldown resistors.
Outputs are designed to perform optimally when AC-
coupled.
The S2004 can be configured for factory test to aid in
functional testing of the device. When in the test
mode, the internal transmit and receive voltage-con-
trolled oscillator (VCO) is bypassed and the reference
clock substituted. This allows full functional testing of
the digital portion of the chip or bypassing the internal
synthesized clock with an external clock source. (See
OTHER OPERATING MODES.)
When operating in the CHAN-LOCK MODE, the user
must insure that the path length of the four high speed
serial data signals are matched to within 50 serial bit
times of delay. Failure to meet this requirement may
result in bit errors in the received data or in byte mis-
alignment.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable deliv-
ery of data and TCLK to the parallel interface, and
before entering the normal operational state of the cir-
cuit. FIFO initialization is performed upon the de-
assertion of the RESET signal. The transmit FIFO is
also reset when the special synchronization pattern
(SYNC=1, DN=1) is generated. TCLKO will operate
normally regardless of the state of RESET.
In addition to path length induced timing skew, the
S2004 can tolerate up to ±3 ns of phase drift between
channels after de-skewing the outputs.
12
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