Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
RECEIVER DESCRIPTION
Data Sheet
Table 6. Lock to Reference Frequency Criteria
Each receiver channel is designed to implement a
Serial Backplane receiver function through the physi-
cal layer. A block diagram showing the basic function
is provided in Figure 5.
Current Lock
State
PLL Frequency
(vs. RFCLK)
New Lock State
Locked
<488 ppm
488 to 732 ppm
>732 ppm
Undetermined
Unlocked
Whenever a signal is present, the receiver attempts to
recover the serial clock from the received data stream.
After acquiring bit synchronization, the S2004
searches the serial bit stream for the occurrence of a
K28.5 character on which to perform word synchroni-
zation. Once synchronization on both bit and word
boundaries is achieved, the receiver provides the
decoded data on its parallel outputs.
Locked
<244 ppm
Locked
244 to 366 ppm
>366 ppm
Undetermined
Unlocked
Unlocked
The S2004 provides the capability to operate with all
four channels locked together (CHANNEL LOCK
mode). Channel lock process and status reporting is
described below.
The ‘lock to reference’ frequency criteria insure that
the S2004 will respond to variations in the serial data
input frequency (compared to the reference fre-
quency). The new Lock State is dependent upon the
current lock state, as shown in Table 6.
Data Input
A differential input receiver is provided for each chan-
nel of the S2004. Each channel has a loopback mode
in which the serial data from the transmitter replaces
external serial data. The loopback function for each
channel is enabled by its respective LPEN input.
The run-length criteria insure that the S2004 will
respond appropriately and quickly to a loss of signal.
The run-length checker flags a condition of consecu-
tive ones or zeros across 12 parallel words. Thus 119
or less consecutive ones or zeros does not cause sig-
nal loss, 129 or more causes signal loss, and 120 –
128 may or may not, depending on how the data
aligns across byte boundaries.
The high speed serial inputs to the S2004 are inter-
nally biased to VDD-1.3V. All that is required externally
is AC-coupling and line-to-line differential termination.
If both the off-frequency detect circuitry test and the
run-length test are satisfied, the CRU will attempt to
lock to the incoming data. When lock is achieved,
LOCK-DET is asserted on the ERR, EOF, and KFLAG
status lines. It is possible for the run length test to be
satisfied due to noise on the inputs, even if no signal is
present. In this case the lock detect status may period-
ically assert as the VCO frequency approaches that of
the REFCLK.
Clock Recovery Function
Clock recovery is performed on the input data stream
for each channel of the S2004. The receiver PLL has
been optimized for the anticipated needs of Serial
Backplane systems. A simple state machine in the
clock recovery macro decides whether to acquire lock
from the serial data input or from the reference clock.
The decision is based upon the frequency and run
length of the serial data inputs. If at any time the fre-
quency or run length checks are violated, the state
machine forces the VCO to lock to the reference clock.
This allows the VCO to maintain the correct frequency
in the absence of data.
In any transfer of PLL control from the serial data to
the reference clock, the RCxP/N outputs remain phase
continuous and glitch free, assuring the integrity of
downstream clocking.
When operating in independent mode, PLL lock status
for each channel is indicated by a 1-0-1 on its respec-
tive ERR, EOF, and KFLAG outputs, respectively.
When operating in the CHANNEL LOCK mode, PLL
locking of all four channels must be accomplished
before byte-skewing is achieved and “in sync” status is
indicated on the ERR, EOF, and KFLAG outputs.
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