Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
Reference Clock Input
“Acquiring Sync” state. K28.5 will be re-ported on each
channel as 0-1-1 (err-eof-kflag).
A single reference clock, which serves both transmitter
and receiver, must be provided from a low jitter clock
source. The frequency of the received data stream
(divided-by -10 or -20) must be within 200 ppm of the
reference clock to insure reliable locking of the
receiver PLL.
When four or more consecutive K28.5 characters are
received on a given channel, the channel will enter the
“Re-sync” state as shown in Figure 8. “Re-sync” state
status will not be reported as 1-1-1 until the first valid
data character has been received. If all four channels
are in the “Re-sync” state and each has received a
valid data character within the deskew time of 5 bytes,
then the S2004 will channel lock by aligning the data
output from each channel such that the first valid data
character for each channel is output simultaneously.
The device will move to the “In Sync” state and indi-
cate channel lock status by each channel as a 0-1-0.
Note that “Re-sync” is reported independently by each
channel regardless of the state of the other channels.
However, “In Sync” can only be reported when all four
channels are in the “In Sync” state and detect a valid
data character within the deskew window. The “In
Sync” state is reported for each as 0-1-0.
Serial to Parallel Conversion
Once bit synchronization has been attained by the
S2004 CRU, the S2004 must synchronize to the 10 bit
word boundary. Word synchronization in the S2004 is
accomplished by detecting and aligning to the 8B/10B
K28.5 codeword. The S2004 will detect and byte-align
to either polarity of the K28.5. Each channel of the
S2004 will detect and align to a K28.5 anywhere in the
data stream. Two modes of operation are supported.
For NORMAL mode operation, the presence of a
K28.5 is indicated for each channel by the assertion of
the EOFx signal.
For CHANNEL-LOCK operation, the S2004 must pro-
vide an additional level of synchronization to in-sure
that differences in delay encountered by the four chan-
nels do not result in parallel output data from each
channel leading or lagging by one parallel clock cycle.
In CHANNEL LOCK, assertion of DNA results in the
K28.5 being transmitted simultaneously on all four
channels. Each receiver provides a FIFO buffer and
adjusts the delay through this buffer to insure that the
first data following the K28.5 is output simultaneously
from the receiver on the parallel interface. The recep-
tion of a K28.5 character is indicated on the EOFA
signal. Table 7 details the function of the EOF, KFLAG,
and ERR pins in status reporting. For CHANNEL-
LOCK operation, a single output clock, RCA P/N, is
provided synchronous with the data. The other RCxP/
N clocks will be frequency locked, but will have an
arbitrary phase relationship with the data.
Once the S2004 has entered the “In Sync” state, it will
report status but will not alter the relative skew of the
output FIFOs. The S2004 will exit the “In Sync” state
and move to the “No Sync” state if one of the four
CRUs reports a loss of lock, if the 8B/10B decoder
observes four consecutive decoding errors, or if the
decoder error rate >50% in a block of 16 codewords.
The device can also be put in the “No Sync” state by
setting TCLKD=Low, asserting RESET, or by momen-
tarily de-asserting CH_LOCK signal.
TCLKD is used to reset the Channel Lock state
machine and provides minimum disruption of the data
path.
When not in Channel Lock Mode, the linkage between
the four state machines is broken and each channel
operates independently.
Loss of Channel Lock will be reported as indicated in
Figure 9 and Table 7 by a 1-0-1 on the ERR, EOF, and
KFLAG signals, respectively. This is during the “No
Sync” state. The status lines will reflect the status of
the individual channels and the device will respond to
appropriate channel locking sequences and deskew
as necessary. Persistence of 1-0-1 status on any
channel is indicative of CRU lock failure, most likely
resulting from loss of receiver input signal. The device
will then respond to the channel locking sequence.
Channel Lock Mode Synchronization
Incidental errors occurring in the received data can
transform a normal data character into a K28.5 char-
acter. To prevent this occurrence from making the
channel locking process unnecessarily vulnerable to
bit errors, the S2004 implements a channel lock state
machine for each channel with linkage between chan-
nels to move to the final de-skewed state.
The Channel Lock state diagram is shown in Figure 8.
The S2004 powers up in the “No Sync” state. When in
the “No Sync” state, each channel of the S2004 is
actively searching the received data stream for the
occurrence of a K28.5 and will align its de-multiplexor
to the character when detected, and will enter the
When operating in the Channel Lock Mode, the
TCLKB input must be tied low.
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