Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
Table 12. MDIO Control Bits Functionality (Continued)
Bit Name
Function
LCKREFN[3:0]
Lock to Reference. Active Low. When active, it forces the REFCLK to LOCK to Reference (REFCLK) for
Channel 0, 1, 2 and 3 respectively.
1 - Default. REFCLK is not locked to the reference clock.
0 - Refclk timing is locked to the ref clock.
CACEN
Reference Clock Coupling Mode. Selects the type of coupling for the Reference Clock input.
1 - Default. AC coupling mode.
0 - DC coupling mode.
RX155EN
MII_ADDR[4:0]
Enable the 155CK[3:0], 155.52 MHz clock output.
1 - On
0 - OFF
This is a read only register set by the MII_ADDR[4:0] pins. See Table 9.
MII_Address based on IEEE 802.3 spec.
SERCLK-
OOFF[3:0]
Serial Clock Off. Active High. When active, this function disables the Serial Clock Outputs (SERCLKOP/
N). This function is controlled by the SERCLKOP/N I/O pin when not in MII Mode.
1 - Default. SERCLK Disabled.
0 - SERCLK Enabled.
TSDEN[3:0]
Enable Serial Data Outputs (SERDATO) and Serial Clock Outputs (SERCLKO) drivers.
1 - On, SERDATOx enabled
0 - OFF, SERDATOx and SERCLKOx disabled
TSCLKOOFF
Disable Transmit Serial Clock Output (TSCLK). Active High. When active, TSCLK is disabled. This func-
tion is controlled by the TSCLKOFF I/O pin when not in MII Mode.
1 - OFF, Default.
0 - On
COREOFF
Disable the CSU core.
1 - CSU Disabled.
0 - Default. CSU Enabled.
COREOFF[3:0] Core Off. Active High. Enabling this function disable the CDR cores for Channel 0, 1, 2 and 3.
1 - Core Disabled.
0 - Default. Core Enabled.
LLEB
PLEB
Normal operation. Loop serial input to the serial output by using the CDR clock for the SERDATA output.
Note: In MII, LLEB mode requires that both LLEB and PLEB are enabled for proper power consumption.
Active Low
1 - OFF, Line loop mode disabled
0 - On, Line loop mode enabled
Loop Enable. Loop serial input to the serial output by using the CSU clock instead of CDR clock for the
SERDATA outputs. PLEB mode is only available in MII mode. PLEB mode disables the SERCLKOP/
N[3:0].
Active Low
1 - OFF, Parallel loop mode disabled
0 - On, Parallel loop mode enabled
FIFOERR[3:0]
(status output)
FIFO Error. Active High. This Read Only register indicates that a FIFO Error event has occurred. This fea-
ture is only available in PLEB mode
1 - FIFO Error currently occurring.
0 - No FIFO Error currently occurring.
22
DS2018
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
