QT2022/32 - Data Sheet: DS3051
11.2.6 8b/10b Error Checkers
For each lane, there is a dedicated 8 bit error counter for checking 8b/10b coding errors on the XAUI input. Each
counter works independently. The error counters are located in bits 7:0 of registers 4.C030h - 4.C033h for Lane0 -
Lane3 respectively. Each register is a read-only, non-rollover counter that is cleared upon read. This counter
should be used when testing with CRPAT and CJPAT.
11.2.7 AMCC XAUI Test Pattern Generator
The XAUI output can be configured to transmit a user-defined 10 bit code word or, alternatively, a static output (no
transitions). Transmission of these test patterns is enabled on a per-lane basis by setting MDIO register bits
4.C010h.3:0 to 1 for Lane3 to Lane0 respectively. The desired pattern is selected on a per-lane basis by setting
MDIO register bits 4.C010h.7:4, where a 1 selects a user-defined pattern and a 0 selects the static output.
The 10-bit user defined test pattern is set in MDIO register bits 4.C011h.9:0. When enabled for a given lane, the
programmed pattern will be continuously transmitted on the RxXAUI output.
11.3 PCS Test Features
11.3.1 Scrambler/Descrambler Bypass Modes
The scrambler can be bypassed by setting the MDIO register bit 3.C000h.2. The descrambler can be bypassed by
setting the MDIO register bit 3.C000h.1.
11.3.2 PCS Jitter Test Pattern Generator
Specific IEEE-standard test patterns are enabled through the MDIO interface by setting the value of bit 3.42.3
(3.2Ah.3), as described in IEEE 802.3-2005 Clause 49.2.8.
By setting MDIO register 3.42.1 (3.2Ah.2) to 1, the output pattern will be a square wave of 8 high cycles followed by
8 low cycles.
If MDIO register 3.42.1 is set to 0, a programmable pseudo-random pattern is generated at the serial output. This
pattern is generated by the scrambler (in figure 2 on page 21) using seeds stored in the MDIO registers 3.34 to
3.41. The scrambler is loaded with a 58-bit seeds at the start of every 128 blocks in the following order: seed A,
seed A Inverted, seed B, seed B Inverted. The data input to the scrambler is set to either all zeros or local fault (LF)
via MDIO register 3.42.0. A control sync header of 01 is used and the payload is the pseudo random data output
from the scrambler.
11.3.3 PCS Jitter Test Pattern Checker
The PCS test pattern checker in the descrambler is enabled via MDIO bit 3.42.2 (3.2Ah.2). When the descrambler
output matches the data pattern, or its inverse, a match is declared. Since the descrambler is free running and the
scrambler is being loaded with a new seed every 128 blocks, a mismatch will be detected once every 128 blocks.
This first mismatch does not increment the counter.
A 16-bit, non-rollover counter, test_pattern_error_count, counts the errors and is reflected in MDIO register 3.43
(3.2Bh). This is a non-rollover counter that is reset when read.
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