QT2022/32 - Data Sheet: DS3051
11.5.1 WIS Square Wave Test Pattern
When the WIS square wave test pattern is enabled, the WIS Transmit block will output a continuous square wave
pattern to the PMA. The square wave pattern is 00FFh (8 consecutive 1s followed by 8 consecutive 0s). Transmis-
sion is enabled by first setting the ‘transmit test pattern enable’ bit 2.7.1 to a 1. Then the square wave pattern is
chosen by setting the ‘test pattern select’ bit 2.7.3 to 1.
There is no pattern checker feature on the receive path for the square wave test pattern.
11.5.2 WIS Mixed Frequency Test Pattern
The mixed frequency test pattern consists of a framed WIS signal with a PRBS23 payload, plus a CID section (con-
secutive identical digits). The PRBS23 pattern is substituted for the payload data that would normally be sent in the
WIS frame. The CID section is selected to stress the lock range of the receiver circuitry, and is placed in the Z0
octet locations as these are not scrambled. The complete Test Signal Structure of the signal is described in IEEE
802.3 Clause 50.3.8.3.
When transmission of the mixed frequency test pattern is enabled, the WIS Transmit block will continuously output
the Test Signal Structure to the PMA. Transmission is enabled by first setting the ‘transmit test pattern enable’ bit
2.7.1 to a 1. Then the mixed frequency test pattern is chosen by setting the ‘test pattern select’ bit 2.7.3 to 0.
When the mixed frequency test pattern is received at the fiber input, errors are detected using the Line BIP Error
Counter registers 2.57 and 2.58 (2.39h and 2.3Ah), the Path Block Error Counter Register 2.59 (2.3Bh) and the
Section BIP Error Counter Register 2.60 (2.3Ch).
The ‘receive test pattern enable’ bit 2.7.2 does not need to be set to 1 to enable error checking.
11.6 Ethernet Packet Generator/Checker (QT2032 and QT2022)
The QT2022/32 has the ability to generate data packets for test purposes. There is one such generator in the TX
path and one in the RX path. To complement the generators, a packet checker is placed in the TX path and another
one in the RX path. See figure 38 on page 97.
11.6.1 General Characteristics
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The packets generated (for Data Fixed Type and Data Incremental Type) are like follows: //S//, //Preamble//
, //D//, ..., //D//, //T//. These packets are not true ethernet packets since they do not include a CRC field,
among other things. However, they are sufficient to test the logic implemented in the QT2022/32.
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Both the TX and RX packet generators share the same control registers with the exception of the enable bit
(reg 3.C020h bits 0 and 1). Thus, they will both output the same type of packets when enabled.
Both the TX and RX packet checkers share the same control registers. Thus, if both checkers are activated,
they will both check for the same type of packets.
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Both the TX and RX packet checkers will be enabled automatically when either packet generator is
enabled.
If neither packet generator is enabled, the packet checkers can be turned on using the enable bits in reg
3.C030h bits 0 and 1. If either bit is set to ‘1’, both TX and RX packet checkers will be enabled.
Since the generators and the checkers have separate controls, it is possible to have the generators send
data other than that expected by the checkers. Intentionally creating error conditions in the checker can be
useful in debugging a chip.
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