QT2022/32 - Data Sheet: DS3051
11.2 XAUI Interface Test Features
11.2.1 XAUI PRBS7 Pattern Generator
7
XAUI PRBS, or XAUI BIST, test mode enables the 2 -1 PRBS generator on the XAUI outputs on each XAUI input
6
7
lane. The PRBS pattern is generated using the polynomial 1+x +x . The generator is enabled by setting MDIO
register bit 4.C000h.10 to a 1. This will cause a PRBS7 pattern to be output on all 4 XAUI output lanes
simultaneously.
11.2.2 XAUI PRBS7 Pattern Checker
For test purposes, there is a PRBS7 pattern checker for each XAUI input lane. The PRBS7 pattern checker
expects data generated using the polynomial 1+x6+x7. The checker is enabled through the MDIO register bit
4.C000h.11. If a pattern error is detected the error flag, MDIO register 4.C001h.3:0, is set for that lane. The error
flag will remain set until cleared by an MDIO read. An 8 bit error counter will also count the total number of errors
for each lane. The error counters are bits 7:0 of registers 4.C030h - 4.C033h for Lane0 - Lane3 respectively. Each
register is a read-only, non-rollover counter that is cleared upon read.
If any of the XAUI input CDRs are not in lock, the PRBS7 pattern checkers will not operate properly for all 4 lanes -
errors will be reported on all lanes. You may check the lock condition for each lane in MDIO register bits
4.C000h.7:4. To avoid this issue, please override the XAUI lane loss-of-lock indication by setting MDIO register bits
4.C020h.11:8 to 1 (for lane3 to lane0 respectively).
11.2.3 XAUI Jitter Test Pattern Generator
There are 3 patterns defined for XAUI interface jitter testing: low frequency (LF), high frequency (HF) and mixed
frequency (MF) test patterns.
Table 41: XAUI Jitter Test Pattern Generator Enable
MDIO register
Test Pattern Select
4.25.1:0
Test pattern enable
4.25.2
Pattern Name
high frequency
low frequency
Repeated Bit Pattern - each lane
10
00
01
10
1
1
1
1111100000
mixed frequency
11111010110000010100
11.2.4 XAUI CRPAT Test Pattern Generator
The continuous random test pattern (CRPAT) consists of a continuous stream of identical packets separated by
minimum IPG. The contents of the packets are as specified in IEEE 802.3 Section 48A.4. The test pattern provides
a broad spectral content and minimal peaking. The CRPAT generator is enabled by writing a 1 to MDIO register
4.C000h.9.
11.2.5 XAUI CJPAT Test Pattern Generator
The continuous jitter test pattern (CJPAT) alternates repeating low transition density patterns with repeating high
transition density patterns. This will expose the receiver’s CDR to large instantaneous phase jumps. The detailed
description of CJPAT is found in IEEE 802.3 Clause 48A.5. The CJPAT generator is enabled by writing a 1 to MDIO
register 4.C000h.8.
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