QT2022/32 - Data Sheet: DS3051
18.5.2 Powerup Reset in a System Application
In a system application (XFP=1), the reset signal must be applied to the TRST_N pin and the RESETN pin after
powerup to guarantee proper operation. The reset signal to the TRST_N pin is required to reset the TAP circuitry.
The reset signal to the RESETN pin is required to reset the Core circuitry.
Figure 59: Powerup Reset in a System Application
COREVDD
24kΩ
active low reset
Circuitry
to TAP
Powerup/Reset
Controller
TRST_N
XFP
active low reset
Circuitry
to Core
RESETN
18.5.3 Valid Startup Sequences
Valid startup sequences are depicted in Figure 60. A hard reset must be applied during the startup sequence. The
hard reset signal must be applied to the TRST_N and/or RESETN pins, as described in Section 18.5.1 or Section
18.5.2, as applicable. The hard reset signal must be held low for a minimum of 500us after the power supplies have
stabilized to acceptable values (as specified in Table 55 on page 187).
A valid Ethernet reference clock must be supplied to the chip before the RESETN signal is pulled high. The chip
can be powered up in low power mode if desired (TXON low). A soft reset is not required but can be applied. A soft
reset cannot be substituted for a hard reset on startup.
In a XENPAK module application, the hard reset must be supplied by a reset controller inside the module in order
to meet the requirement specified in XENPAK MSA Figure 16.
Figure 60: Valid Startup Sequences
t=0
(Power applied)
ON
EREFCLK
OFF
Vih
TXON
Vil
Vih
TRST_N/RESETN
Vil
“1”
MDIO
(x.0.15)
Note: Soft reset is self-clearing
“0”
PHY not
ready
PHY ready
outputs enabled
Soft resets are not required to complete the startup sequence. However, the startup sequence
is compatible with soft resets.
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