QT2022/32 - Data Sheet: DS3051
18.2 Loop Filter Component Selection
The receive PLL components (connected to the RXFN/P pins in Figure 57) and the transmit PLL components (con-
nected to the TXFN/P pins in Figure 57) must be selected carefully. Due to the sensitivity of these circuits, AMCC
recommends thin film capacitors instead of the more common ceramic capacitors. Ceramic capacitors are known
to exhibit a piezoelectric effect, most often observed during temperature cycling. The voltage spikes caused by a
ceramic capacitor can adversely affect the PLL performance, potentially inducing errors on the traffic.
For further information on the piezoelectric effect, please read the Application Note, “Piezoelectric Effect in
Ceramic Capacitors” at www.atceramics.com.
18.3 Power Supply Filtering and Decoupling
Power supply filtering recommendations are provided in a separate Application Note. Please contact AMCC for fur-
ther information.
18.4 Dual 10GE & 10GFC Rate Support
With the QT2022/32, a module or system card can be designed that will support both the 10GE and 10GFC rates
in a single design. This is accomplished by configuring the TXPLLOUT pins as clock inputs. Two reference clocks
can be supplied to the chip, one at 156.25MHz (for 10GE) and the other at 159.375MHz (for 10GFC). One clock
can be connected to the standard EREFCLK input and the other to the TXPLLOUT input.
By default, the EREFCLK input is selected. By setting MDIO Register bit 1.C001h.7 to 1, the reference clock sup-
plied to the TXPLLOUT pins will be selected and the clock signal on the EREFCLK input is ignored. Either input
may be used for the two different clocks. Device jitter performance is the same with both inputs.
To minimize module power consumption and to prevent coupling, the unused oscillator should be powered down
using the GPIO drivers (LED1, LED2 or LED3). One GPIO output can be used to drive the enable/disable pin for
each oscillator.
Clock input selection requires an MDIO command. The default settings can be modified by taking advantage of the
extended EEPROM memory support. Please see Section 10.7, “Register Configuration from External EEPROM,”
on page 91 for details.
18.5 Reset Requirements
18.5.1 Powerup Reset in a Module Application
In a module application (XFP=0), the reset signal must be applied to the TRST_N pin after powerup to guarantee
proper operation. This will reset the TAP circuitry and the Core Circuitry inside the chip. A reset signal must be
applied after hotplug and should be provided by a powerup/reset controller inside the module. The reset signal
from the module edge connector can be applied to the TRST_N signal, as shown in Figure 58. The module reset
signal can also be applied directly to the RESETN pin.
The TAP port requires a reset only on powerup. It does not need to be reset afterwards for proper operation of the
chip and therefore does not need to be connected to the module edge connector RESET signal.
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