QT2022/32 - Data Sheet: DS3051
18.9 Jumbo Frame Support and Round-Trip Delay in WAN Applications
The default startup configuration of the QT2032 supports jumbo frame transmission (10kB frame size). This is sup-
ported in both WAN and LAN modes. When operating in WAN mode, the round-trip delay time of the chip exceeds
1
the IEEE requirement of 14336 bit times (BT) specified in Clause 50.3.7. The delay constraints of the QT2022/32
are presented in Table 75 on page 202.
The QT2032 can be programmed to comply with the IEEE round-trip delay constraints. However, in doing so jumbo
frames are not supported. Table 76 on page 216 provides the necessary information to program the chip to meet
the delay constraints. All registers listed in the table must be set to guarantee the specified delay constraint.
Register bit 4.C050h.0 is an enable bit. The enable bit must be set last when reprogramming the delay constraints.
When this bit is set to ‘0’, the chip will operate in its default mode i.e. it will support jumbo frames. .
Table 76: Register Values for Round-Trip Delay Compliance
Values to Meet IEEE Round-Trip Delay Constraint in WAN mode
Register Address
(max. 2kB Packets)
4.C041h
4.C042h
4.C043h
4.C044h
4.C045h
0x0000
0x00F8
0x0002
0x000B
0x0001
4.C051h
4.C052h
4.C053h
4.C054h
4.C055h
0x0004
0x00FD
0x006E
0x00FD
0x0078
4.C051h
0x0001
18.10 DOM Memory Behavior
The DOM memory definition is presented in Table 27 and Table 28 of the XENPAK MSA. Most of the defined fields
store 16-bit values that span two I2C addresses. To ensure partially updated fields are not read over the MDIO
2
bus , the QT2022/32 organizes the DOM memory into pairs. When an MDIO command reads an even-numbered
address location in the DOM memory range 1.A000h-1.A0FFh, the register at the next higher MDIO address will be
latched. This means that the current value will not be updated to show a newer value, even if the peripheral DOM
device is read again. The latched odd register address will be unlatched by two (or more) successive MDIO reads.
The most recently read value from the DOM device on the I2C interface is buffered in internal memory. MDIO reads
of the even address will update the associated odd MDIO register with the most recent value.
This is expected behavior for most of the defined registers in this space, which store 16-bit fields that span two
addresses. MDIO reads from these memory addresses must be performed in pairs to upload the full 16-bit field.
This is not expected behavior for MDIO Registers 1.A070h - 1.A071h and 1.A074h - 1.A075h. These registers do
not store fields that span two registers. To ensure MDIO reads to the odd addresses report the current value, per-
form MDIO reads in pairs. Read the associated even address first. Alternatively, read each odd register twice.
The contents of register 1.A071h feed into the LASI alarm. Note that the internally buffered memory value is used
to drive the LASI alarm. The LASI alarm will trigger as expected, even if the MDIO register is latched with an old
value.
1. The bit time (BT) is the reciprocal of the bit rate. For 10GE, 1 BT = 100ps. See IEEE 802.3-2002 Clause 1.4.50 for more details.
2. In particular, if the MSB of a two-byte field is read over the MDIO bus while a DOM update is in progress, the LSB may be updated before it
is read over the MDIO bus, such that the LSB and MSB contain values from two different DOM read events.
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