QT2022/32 - Data Sheet: DS3051
10GBASE-R
PCS Test
Pattern Error
Counter
Register 3.43
(3.2Bh)
10GBASE-R
PCS BER Timer
Value Register
3.C001h
10GBASE-R PCS Jitter
Test Pattern Control
Register 3.42 (3.2Ah)
PCS Vendor
Specific
3.C006h
PCS Vendor Specific
3.C000h
Bit
0
pattern select, RW
1=zeros data pattern
0=LF data pattern
Test pattern error
count, RO/NR count
reset on read
64/66 encoder error detected,
RO/LH
1 = error
BER Timer
Counter Start
Value
receive frame off-
set, RO
LSB is bit 0
MSB is bit 15
default value =
100 d = 64 hex
1
test pattern select, RW
1 = square wave test pattern
0= pseudo random test pat-
tern
RX descrambler bypass, RW
1 = bypass
0 = not bypassed (default)
2
3
Receive test pattern enable,
RW
1=enable receive test
TX scrambler bypass, RW
1=bypass
0 = not bypassed (default)
Transmit test pattern enable,
RW
reset receive pcs, RW
0=reset
1=enable transmit test
1=not reset, default
Note: not self clearing
4
5
Transmit PRBS31 generator
enable, RW
0 = not enabled, default
1 = enable Tx PRBS31
reset transmit pcs, RW
0=reset
1=not reset, default
Note: not self clearing
Receive PRBS31 checker
enable, RW
PCS loopback data out ena-
ble, RW
0 = not enabled, default
1 = enable Rx PRBS31
checker
1=transmit data at TXOUT
when in PCS loopback mode
0=transmit all a square wave
when in PCS loopback mode
6
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
7
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
8
9
10
11
12
BER TEST enable, RW
0 = disabled, default
1 = enabled
13
14
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
BER Test in progress, RO
1 = BER Test in progress
15
Reserved, RO
BER Test Complete, RO/LH
1 = BER Test Completed
Reserved, RO
168
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