QT2022/32 - Data Sheet: DS3051
13 QT2022/32 MII Register Map
The QT2022/32 implements the following register maps defined by the IEEE 802.3 Specification, Clause 45:
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•
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10G PMA/PMD (device 1)
10G WIS (device 2) - QT2032 only
10G PCS (device 3)
10G PHY XGXS (device 4)
As well, there are a number of vendor specific registers which are used for additional functionality, testability and
observability.
All reserved/undefined registers are read as 0. Writes to undefined registers are ignored.
Type Name
Type Definition
RO
read only register with a defined function
writes are ignored
RO/LL
RO/LH
read only register, latched low
bit is reset to high by a read unless the input low state is present
read only register, latched high
bit is reset to low by a read unless the input high state is present
RO/NR
RW
Read Only Register, Non-rollover counter. Cleared on read.
read/write register with a defined function
RW, SC
self clearing read/write register
bit clears itself after its defined function has been completed; use for resets
RW, Prot
R/W register which can be made R/O by setting EEPROM_PROT=0
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