QT2022/32 - Data Sheet: DS3051
Table 51: RMDIO START Block Format
Input Data
Sync
bits
Block Payload
C C C C /
10
8’h1e
7’h00
7’h00
7’h00
7’h00
7’h69
7’h78
7’h66
7’h33
7’h33
0
1 2 3
C C C C
5 6 7
4
Table 52: RMDIO TERM Block Format
Input Data
Sync
bits
Block Payload
C C C C /
10
8’h1e
7’h00
7’h00
7’h00
7’h00
7’h70
7’h78
7’h66
0
1 2 3
C C C C
5 6 7
4
Table 53: RMDIO Data Block Format
Input Data
Sync
bits
Block Payload
D D D D /
01
Ctrl/Stat[7:0]
Device[7:0]
Reg Addr[15:0]
Data [15:0]
Rsvd[15:0]
0
1 2 3
D D D D
5 6 7
4
Ctrl/Stat field:
•
•
•
bit [0] - Read/Write Request (read = 1, write = 0)
bit [6:1] - Reserved
bit [7] - Response bit (request = 0, response = 1)
Device Address field:
•
•
bit [5:0] - Device Address (valid only for request - all 0s for response)
bit [7:6] - Reserved
Register Address field:
•
bit [15:0] - Register Address (valid only for request - all 0s for response)
Data Field:
•
bit [15:0] - MDIO Data (valid only for response - all 0s for request)
12.8 PRBS Performance Monitoring
The Extended Link Monitoring feature includes the capability to monitor link quality. This is achieved by generating
and checking special pseudo-random 66b blocks in the IPG. The pseudo-random block consists of a 64b word plus
2 sync bits. The 64b word is composed of either all 1s or all 0s which is then scrambled before transmission, using
the scrambling algorithm presented in figure 3 on page 23. The sync bits are not scrambled.
The QT2022/32 will begin sending pseudo-random blocks within the IPG on the fiber output when MDIO register bit
3.CC03h.0 is set to 1. The chip will alternate sending all 1s and all 0s blocks. The number of transmitted pseudo-
random blocks is counted in MDIO register 3.CC04h. This is a 16 bit rollover counter that is cleared on read.
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