QT2022/32 - Data Sheet: DS3051
Transmission of the pseudo-random blocks cannot be enabled unless the ‘AMCC part detected’ bit 3.CC01h.0 is
set to 1. When the ‘Extended Link Monitoring RX Enable’ bit 3.CC00h.1 is set to 1 (0 by default), any pseudo-ran-
dom blocks detected by the QT2022/32 on the serial receive input are replaced with idle codes. Ensure this bit is
set to force idle replacement.
The chip will begin counting and checking the pseudo-random blocks for errors when MDIO register bit 3.CC03h.1
is set to 1. The number of received pseudo-random blocks is counted in MDIO register 3.CC05h. The chip also
checks the descrambled 66b code for errors, which are counted in MDIO register 3.CC06h.
The received block counter and error counter are linked to allow an accurate error rate calculation. A read of the
block counter will latch both registers, thereby stopping both registers from counting. The error counter can now be
read and an accurate block error rate can be calculated. Reading the error counter clears both counters and
restarts them.Both counters are 16 bits read only.
By setting MDIO register bit 3.CC03h.2 to 1, the chip will generate a single corrupted pseudo-random block (if
transmission is enabled). This can be used to verify the errored block counter is operating properly.
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