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PPC440SPE-AGB533C 参数 Datasheet PDF下载

PPC440SPE-AGB533C图片预览
型号: PPC440SPE-AGB533C
PDF下载: 下载PDF文件 查看货源
内容描述: 440SPe的PowerPC嵌入式处理器 [PowerPC 440SPe Embedded Processor]
分类和应用: PC
文件页数/大小: 80 页 / 1204 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.23 - Sept 21, 2006  
PowerPC 440SPe Embedded Processor  
Initialization  
Preliminary Data Sheet  
The PPC440SPe provides the option for setting initial parameters based on default values or by reading them from  
a serial “bootstrap” ROM attached to the IIC0 bus. These options are defined by strapping on three external pins  
(see “Strapping” below).  
Strapping  
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default  
initial conditions prior to PPC440SPe start-up. The actual capture instant is the nearest SysClk edge before the  
deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)  
resistors to select the desired default conditions. They are used for strap functions only during reset. Following  
reset they are used for normal functions.  
The following table lists the strapping pins along with their functions and strapping options:  
Table 21. Strapping Pin Assignments  
Pin Strapping  
Bit 1  
Bit2  
Function  
Option  
Bit 0  
H13  
(UART0_DCD)  
C12  
(UART0_DSR)  
B08  
(UART0_CTS)  
Serial Bootstrap ROM is disabled (Bit 0 off).  
Refer to the IIC Bootstrap Controller chapter in the  
PPC440SPe Embedded Processor User’s Manual  
for details.  
Boot from EBC  
Boot from PCI  
0x54  
0
0
1
0
1
0
Serial Bootstrap ROM is enabled (Bit 0 on).  
The options being selected are the IIC0 slave  
address that responds with strapping data and  
reading 128 bits from the Bootstrap ROM.  
0
0
1
1
0x50  
0x54  
0x50  
1
1
1
1
0
1
Serial Bootstrap ROM is enabled (Bit 0 on).  
The options being selected are the IIC0 slave  
address that responds with strapping data and  
reading 256 bits from the Bootstrap ROM.  
Serial Bootstrap ROM  
During reset, if the serial device is enabled, initial conditions can be read from a ROM connected to the IIC0 port. In  
this case, at the de-assertion of SysReset, the PPC440SPe sequentially reads up to 32 bytes from the ROM device  
on the IIC0 port and sets the SDR0_SDSTP0 - SDR0_SDSTP7 registers accordingly.  
The initialization settings and their default values are covered in detail in the PPC440SPe Embedded Processor  
User’s Manual.  
AMCC Proprietary  
77  
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