Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
The following example shows the timing relationship between SDRAM DDR Data at the input pin and the store of
the Data in stage 1.
Figure 11. DDR SDRAM Read Cycle Timing—Example
Oversampling Guard Band
DDR 1X Clock
DDR 2X Clock
Memclk (Diff.)
DQS at
MemCntl Pin
Data at Pin
D0
D1
D2
D3
D4
T2
D5
D6
D7
D8
D9
Store 1st Data in Stage 2
T3
Feedback
Output
1X DDR Clk cycle
T1
T4
Delayed DQS
Data Out Stage 1 (0)
Data Out Stage 1 (1)
Data out Stage 1 (2)
Valid
High
Low
D0
D1
D2
D3
Data Out Stage 2
PLB 1X Clock
76
AMCC Proprietary