Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Input/Output Timing
These timing diagrams illustrate the relationship of the timing parameters defined in the I/O Specification tables
that follow.
Figure 5. Input Setup and Hold Timing Waveform
Clock
T
min
IS
T
min
IH
Inputs
Valid
Figure 6. Output Delay and Hold Timing Waveform
Clock
max
min
max
max
min
T
T
T
OV
OV
OV
T
T
min
T
OH
Outputs
OH
OH
High (Drive)
Float (High-Z)
Valid
Valid
Low (Drive)
AMCC Proprietary
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