Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Table 14. I/O Specifications—All Speeds
(Sheet 3 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz
and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time
requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
3. These are DDR signals that can change on both the positive and negative clock transitions.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(TOH min)
(TIS min)
(TIH min)
(TOV max)
System Interface
Halt
n/a
n/a
n/a
n/a
n/a
n/a
n/a
19.1
n/a
n/a
8.7
n/a
8.7
n/a
n/a
8.7
n/a
n/a
async
async
n/a
GPIO00:31
SysClk
SysErr
n/a
n/a
19.1
n/a
async
async
async
async
async
n/a
SysPartSel
SysReset
HISRRst
TestEn
n/a
19.1
n/a
n/a
n/a
n/a
n/a
TmrClk
n/a
Trace Interface
TrcClk
n/a
n/a
19.1
19.1
19.1
19.1
8.7
8.7
8.7
8.7
TrcBS0:2
TrcES0:4
TrcTS0:6
74
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