Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Table 15. I/O Specifications—533MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(TOH min)
(TIS min)
(TIH min)
(TOV max)
External Slave Peripheral Interface
PerAddr00:23
PerBE0
n/a
1
6.2
0
19.1
27.7
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
8.7
12.8
8.7
8.7
8.7
8.7
8.7
8.7
8.7
8.7
8.7
8.7
8.7
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
n/a
PerBLast
PerCS0:2
PerData0:7
PerOE
n/a
n/a
1.2
n/a
1.7
3.6
n/a
n/a
n/a
n/a
1.2
1
n/a
1
5.7
5.9
6
n/a
0
0
n/a
1
5.8
5.7
n/a
5.7
5.7
n/a
n/a
n/a
0
PerPar0
PerReady
PerR/W
n/a
n/a
n/a
0
1
1
PerWE
n/a
n/a
n/a
ExtReset
PerClk
n/a
n/a
n/a
PerClk
PLB clk
PerClk
PerErr
AMCC Proprietary
75
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
