Revision 1.19 – May 07, 2008
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Table 20. I/O Specifications—PCI, UART, IIC, SPI, Ethernet, System and Debug Interfaces (Sheet 2 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. EMCSync is a weak driver. Redrive EMCSync when driving more than one load.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
(TIS min)
(TIH min)
Ethernet SMII Interface
EMC0RxD
1.5
1.5
1
1
5.1
5.1
5.1
5.1
5.1
6.8
6.8
6.8
6.8
6.8
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
1
1
EMC0TxD
3.5
0
EMC1RxD
1
EMC1TxD
3.5
3.5
0
0
1
EMCSync
1, 2
Internal Peripheral Interface
IIC0SClk
n/a
n/a
n/a
n/a
n/a
n/a
n/a
na
10.2
10.2
10.2
10.2
10.2
10.2
10.2
na
IIC0SData
IIC1SClk
5
5
0
0
IIC0Clk
IIC1Clk
IIC1SData
SCPClkOut
SCPDI
7
2
SCPClkOut
SCPClkOut
SCPDO
6
0
UARTn_Rx
UARTn_Tx
UARTn_DCD
UARTn_DSR
UARTn_CTS
UARTn_DTR
UARTn_RI
UARTn_RTS
Interrupts Interface
IRQ0:9
async
async
async
async
async
async
async
async
10.3
na
7.1
na
na
na
na
na
10.3
na
7.1
na
10.3
7.1
na
na
async
JTAG Interface
TCK
na
na
na
na
async
async
async
async
async
TDI
TDO
15.3
na
10.2
na
TMS
TRST
na
na
System Interface
SysReset
na
na
na
na
async
async
async
Halt
SysErr
10.3
10.3
7.1
7.1
GPIO00:63
Trace Interface
TrcClk
10.3
10.3
10.3
10.3
7.1
7.1
7.1
7.1
TrcBS0:2
TrcClk
TrcClk
TrcClk
TrcES0:4
TrcTS0:6
74
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
