Revision 1.19 – May 07, 2008
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Table 20. I/O Specifications—PCI, UART, IIC, SPI, Ethernet, System and Debug Interfaces (Sheet 1 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. EMCSync is a weak driver. Redrive EMCSync when driving more than one load.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
(TIS min)
(TIH min)
PCI Interface
PCIAD31:00
PCIC3:0/BE3:0
PCIDevSel
PCIFrame
PCIGnt0:5
PCIIDSel
5
5
5
5
0
0
0
0
6
6
6
6
6
2
2
2
2
2
0.5
0.5
0.5
0.5
0.5
n/a
0.5
0.5
0.5
0.5
n/a
n/a
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
n/a
1.5
1.5
1.5
1.5
n/a
n/a
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
5
0
PCIINT
6
6
6
6
2
2
2
2
async
PCIIRDY
5
5
5
5
0
0
0
0
PCIPar
PCIPErr
PCIReq0:5
PCIReset
PCISErr
5
5
5
0
0
0
6
6
6
2
2
2
PCIStop
PCITRDY
Ethernet MII Interface
EMCCD
10
10
10
10
10
10
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
n/a
5.1
5.1
5.1
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
n/a
6.8
6.8
6.8
1, async
1, async
EMCCrS
EMCDV
EMCMDClk
EMCMDIO
EMCRxClk
EMCRxD0:3
EMCRxErr
EMCTxClk
EMCTxD0:3
EMCTxEn
EMCTxErr
1, async
EMCMDClk
1
1, async
10
10
10
10
EMCRxClk
EMCRxClk
1
1
1, async
20
20
20
0
0
0
EMCTxClk
EMCTxClk
EMCTxClk
1
1
1
for MII,
RMII,
SMII
RejectPkt
3
1
EMCRxClk
Ethernet RMII Interface
EMC0CRSDV
EMC0RxD0:1
EMC0RxErr
4
4
4
2
2
2
5.1
5.1
5.1
6.8
6.8
6.8
EMCRefClk
EMCRefClk
EMCRefClk
1
1
1
EMC0TxD0:1
EMC1CRSDV
EMC1RxD0:1
EMC1RxErr
12.5
12.5
0
0
4
4
4
2
2
2
5.1
5.1
5.1
6.8
6.8
6.8
EMCRefClk
EMCRefClk
EMCRefClk
1
1
1
EMC1TxD0:1
AMCC Proprietary
73
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
