Revision 1.19 – May 07, 2008
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
DDR SDRAM Write Operation
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 9. DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut0
MemClkOut0(90)
T
SA
Addr/Cmd
T
DS
T
T
SK
DS
T
HA
DQS
T
SD
T
SD
MemData
T
HD
T
HD
T
= Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)
= Setup time for address and command signals to MemClkOut0(90)
SK
T
SA
T
= Hold time for address and command signals from MemClkOut0(90)
HA
SD
HD
DS
T
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
T
T
Note: The timing data in the following tables is based on simulation runs using Einstimer.
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