Revision 1.19 – May 07, 2008
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
I/O Specifications
Table 19. Peripheral Interface Clock Timings
Parameter
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
PCIClk input high time
Min
Max
Units
MHz
ns
Notes
–
66.66
15
–
40% of nominal period
60% of nominal period
ns
PCIClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
MHz
ns
400
–
EMCMDClk output high time
EMCMDClk output low time
EMCTxClk input frequency MII
EMCTxClk period MII
160
–
ns
160
–
ns
2.5
25
MHz
ns
40
35% of nominal period
35% of nominal period
2.5
400
EMCTxClk input high time
–
ns
EMCTxClk input low time
–
ns
EMCRxClk input frequency MII
EMCRxClk period MII
25
400
MHz
ns
40
EMCRefClk input frequency RMII (SMII)
EMCRefClk period RMII (SMII)
EMCRefClk input high time
EMCRefClk input low time
50 (125)
50 (125)
MHz
ns
2
20 (8)
20 (8)
35% of nominal period
35% of nominal period
65% of nominal period
65% of nominal period
ns
ns
70
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
