Revision 1.19 – May 07, 2008
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Table 19. Peripheral Interface Clock Timings (Continued)
Parameter
Min
Max
–
Units
ns
Notes
EMCRxClk input high time
EMCRxClk input low time
35% of nominal period
35% of nominal period
–
ns
PerClk (and OPB Clock) output frequency (for ext. master or
sync. slaves)
33.33
66.66
MHz
PerClk period
15
30
ns
ns
ns
PerClk output high time
PerClk output low time
50% of nominal period
33% of nominal period
66% of nominal period
50% of nominal period
1000 / (2TOPB1+2ns)
UARTSerClk input frequency
UARTSerClk period
–
MHz
ns
1
2TOPB+2
–
–
1
1
1
2
T
OPB+1
UARTSerClk input high time
ns
TOPB+1
UARTSerClk input low time
TmrClk1 input frequency
TmrClk1 period
–
ns
MHz
ns
–
100
10
–
TmrClk1 input high time
TmrClk1 input low time
Notes:
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock
frequency is 66.66 MHz.
2. In RMII mode, 50MHz +/- 50PPM input EMCRefClk is required. In SMII mode, a 125 MHz +/- 100PPM input EMCRefClk is required.
Figure 6. Input Setup and Hold Waveform
Clock
1.25V
T
min
IS
T
min
IH
Inputs
Valid
AMCC Proprietary
71
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
