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PPC440GP-3RC400C 参数 Datasheet PDF下载

PPC440GP-3RC400C图片预览
型号: PPC440GP-3RC400C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 440GP嵌入式处理器 [Power PC 440GP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 83 页 / 1393 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – October 4, 2007  
440GP – Power PC 440GP Embedded Processor  
Data Sheet  
Example 3:  
In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system  
will still work, but there will be more latency before the data is sampled into RDSP. Again, T = 1.5ns and T  
=
T
TE  
4.3ns at worst case conditions.  
DDR SDRAM Read Cycle Timing—Example 3  
DQS at pin  
Data at pin  
D0  
D1  
D3  
D2  
T
SIN  
DQS Stage 1 C  
Data in Stage 1 D  
D0  
D1  
D3  
D2  
T
DIN  
T
P
High  
Low  
D0  
D1  
D2  
D3  
Data out Stage 1  
D0  
D2  
PLB Clock  
Read Clock Delayed  
T
P
D0  
D1  
High  
D2  
D3  
Data out Stage 2  
Low  
High  
Low  
D2  
D3  
D0  
D1  
Data out Stage 3  
with ECC  
T
TE  
High  
Low  
D0  
D1  
D2  
D3  
Data in at RDSP  
with ECC  
High  
Low  
D0  
D1  
D2  
D3  
Data out RDSP  
with ECC  
(3)  
T = Propagation delay from Stage 2 input to RDSP input w/o ECC  
T
T
= Propagation delay from Stage 2 input to RDSP input with ECC  
TE  
AMCC  
79  
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