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PPC440GP-3RC400C 参数 Datasheet PDF下载

PPC440GP-3RC400C图片预览
型号: PPC440GP-3RC400C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 440GP嵌入式处理器 [Power PC 440GP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 83 页 / 1393 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – October 4, 2007  
440GP – Power PC 440GP Embedded Processor  
Data Sheet  
DDR SDRAM MemClkOut0 and Read Clock Delay  
PLB Clk  
MemClkOut0(0)  
T
MD  
T
min = 850ps  
MD  
T
max =  
2600ps  
MD  
Read Clock  
T
RD  
T
min =  
0ps  
RD  
T
max =  
300ps  
RD  
In operation, following the receipt of an address and read command from the PPC440GP, the SDRAM generates  
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GP using a DQS  
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs  
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to  
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of  
Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.  
DDR SDRAM Read Data Path  
Mux  
RDSP  
FF  
Package pins  
Q
D
PLB bus  
ECC  
Stage 3  
Stage 1  
Stage 2  
Q
D
Q
D
D
Q
C
FF,  
XL  
FF  
FF  
Data  
C
C
C
Read Select  
(SDRAM0_TR1)  
1/4  
Cycle  
Delay  
Programmed  
Read Clock  
Delay  
DQS  
PLB Clock  
FF Timing:  
T
T
T
= Input setup time = 0.2ns  
= Input hold time = 0.1ns  
= Propagation delay (D to Q or C to Q) =  
FF: Flip-Flop  
XL: Transparent Latch  
IS  
IH  
0.6ns maximum  
P
AMCC  
75  
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