Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment (Sheet 5 of 6)
Ball
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
Signal Name
Ball
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
Signal Name
Ball
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
Signal Name
MemData58
Ball
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Signal Name
MemData51
TmrClk
MemData55
OVDD
GND
UART0_DSR
DM7
MemData53
DM6
PerCS7
OVDD
MemData59
GND
PerCS2
DQS6
MemData63
GND
Halt
MemData62
VDD
WE
MemData60
MemData54
MemClkOut0
MemClkOut0
MemAddr12
MemAddr9
MemData31
MemAddr8
MemData26
MemData19
MemData09
MemData05
IRQ10 *
MemData46
MemData43
MemData47
ClkEn2
MemData57
VDD
ECC3
GND
ECC4
ClkEn3
SVDD
GND
MemData34
MemAddr11
MemData30
MemData27
MemAddr7
MemData23
MemData20
MemData10
MemData13
MemAddr00
MemAddr02
HoldAck
MemData36
SVDD
MemData32
GND
VDD
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
GND
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
MemData21
SVDD
BankSel1
GND
MemData04
GND
MemAddr10
SVDD
PerClk
MemData08
GND
OVDD
PerWBE1
PerAddr29
PerAddr31
TCK
PerPar3
GND
PerPar2
VDD
PerAddr26
VDD
PerWBE2
GND
TDO
PerAddr30
UART0_DCD
HoldReq
PerAddr27
PerWBE3
TDI
44
AMCC