Revision 1.29 – May 07, 2008
440EP – PPC440EP Embedded Processor
Data Sheet
Table 17. Clocking Specifications
Symbol
SysClk Input
FC
Parameter
Min
Max
Units
Frequency
Period
33.33
66.66
30
MHz
ns
TC
15
TCS
TCH
TCL
Edge stability (cycle-to-cycle jitter)
–
±0.15
ns
High time
Low time
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
Note: Input slew rate ≥ 1V/ns
CPU Clock
FC
MemClkOut and PLB Clock
Frequency
333
667
FC
TC
Frequency
Period
100
7.5
133.33
10
MHz
ns
TCH
High time
45% of nominal period
55% of nominal period
ns
PLL VCO
FC
Frequency
Period
600
1334
1.66
MHz
ns
TC
0.7496
TrcClk
FC
CPU FC/4
CPU FC/4
Frequency
MAL Clock
FC
Frequency
Period
45
12
83.33
22.2
MHz
ns
TC
Figure 5. Timing Waveform
1.7V (1.8 V)
1.25V (1.5V)
0.7V (0.8V)
T
T
CL
CH
T
C
Note: SysClk is a 2.5V/3.3V tolerant receiver. Slew rate should be measured between 0.7V and 1.7V.
AMCC Proprietary
67
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
