Revision 1.29 – May 07, 2008
440EP – PPC440EP Embedded Processor
Data Sheet
• All wire of the filter circuit should be kept as short as possible to minimize coupling from other signals.
• AGND (SAGND) must be connected to the digital ground plane at the AVDD (SAVDD) capacitor.
• The impedance of the ferrite bead should be much greater than that of the capacitor at frequencies where noise is
expected.
AVDD, SAVDD
VDD
L – SMT ferrite bead chip, Murata BLM21PG600SN1
L
C – 0.1μF ceramic
C
AGND, SAGND
GND
Table 12. Input Capacitance
Parameter
Symbol
Maximum
2.5
Unit
pF
pF
pF
pF
pF
pF
Notes
CIN1
Group 1 (2.5V SSTL I/O)
Group 2 (3.3V LVTTL I/O)
Group 3 (PCI I/O)
CIN2
CIN3
CIN4
CIN5
CIN6
2.1
2.5
Group 4 (Receivers)
0.9
Group 5 (3.3V tolerant CMOS I/O)
Group 6 (USB)
2.4
4.5
Table 13. Typical DC Power Supply Requirements
+1.5V Supply
(VDD+AVDD+SAVDD
+2.5V Supply
+3.3V Supply
Frequency (MHz)
Total
Unit
Notes
)
(SVDD
)
(OVDD)
333
400
533
667
1.15
1.24
1.43
2.08
1.15
1.15
1.15
1.15
0.04
0.04
0.04
0.04
2.34
2.43
2.62
3.27
W
W
W
W
1
1
1
1
Notes:
1. Typical Power is based on nominal voltage of VDD = +1.5V and TC = max. specified in Table 10 on page 61, while running Linux and a
test application that exercises each core with representative traffic.
64
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