Revision 1.29 – May 07, 2008
440EP – PPC440EP Embedded Processor
I/O Specifications
Data Sheet
Table 18. Peripheral Interface Clock Timings
Parameter
Min
–
Max
Units
MHz
ns
Notes
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
66.66
15
–
PCIClk input high time
40% of nominal period
60% of nominal period
ns
PCIClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
MHz
ns
400
–
EMCMDClk output high time
EMCMDClk output low time
EMCTxClk input frequency MII
EMCTxClk period MII
160
–
ns
160
–
ns
2.5
25
MHz
ns
40
400
EMCTxClk input high time
EMCTxClk input low time
EMCRxClk input frequency MII
EMCRxClk period MII
35% of nominal period
35% of nominal period
2.5
–
ns
–
ns
25
MHz
ns
40
400
EMCRxClk input high time
EMCRxClk input low time
EMCRefClk input frequency RMII (SMII)
EMCRefClk period RMII (SMII)
EMCRefClk input high time
EMCRefClk input low time
35% of nominal period
35% of nominal period
50 (125)
–
ns
–
ns
50 (125)
MHz
ns
2
20 (8)
20 (8)
35% of nominal period
35% of nominal period
65% of nominal period
65% of nominal period
ns
ns
PerClk (and OPB clock) output frequency (for ext. master or
sync. slaves)
33.33
66.66
MHz
PerClk period
15
30
ns
ns
ns
PerClk output high time
PerClk output low time
50% of nominal period
33% of nominal period
66% of nominal period
50% of nominal period
1000 / (2TOPB1+2ns)
UARTSerClk input frequency
UARTSerClk period
–
MHz
ns
1
1
1
1
2TOPB+2
–
–
T
OPB+1
OPB+1
UARTSerClk input high time
ns
T
UARTSerClk input low time
USB2Clk input frequency
USB1Clk input frequency
–
ns
60
48
60
48
MHz
MHz
AMCC Proprietary
69
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
